ST16C550 Exar Corporation, ST16C550 Datasheet - Page 16

• Manufacturer Part Number: ST16C550
• Description: UART WITH 16-BYTE FIFO
• Manufacturer: Exar Corporation

ST16C550
Interrupt Status Register (ISR)
The ST16C550 provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR
will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. Whenever
the interrupt status register is read, the interrupt status
is cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after rereading the interrupt
status bits. The Interrupt Source Table 5 (below) shows
the data values (bit 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of
these interrupt levels:
Priority
Level
Rev. 4.30
X
1
2
2
3
4
Table 5, INTERRUPT SOURCE TABLE
Bit-3 Bit-2 Bit-1 Bit-0
0
0
0
1
0
0
[ISR]
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
No interrupt pending
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
Source of the interrupt
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