BT16260DGG Philips Semiconductors, BT16260DGG Datasheet - Page 2

• Manufacturer Part Number: BT16260DGG
• Description: 12-bit to 24-bit multiplexed D-type latches 3-State
• Manufacturer: Philips Semiconductors

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN DESCRIPTION
Philips Semiconductors
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
1998 Feb 10
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model (C = 200pF, R = 0).
Latch-up performance exceeds 500mA per JEDEC Standard
JESD-17.
Distributed V
switching noise.
Flow-through architecture optimizes PCB layout.
High-drive outputs (–32mA I
74ABTH16260 incorporates bus-hold inputs which eliminate the
need for external pull-up resistors.
Package options:
– 56-pin plastic Shrink Small-Outline Package (SSOP)
– 56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
12-bit to 24-bit multiplexed D-type latches (3-State)
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
SYMBOL
C
t
t
I
C
CCZ
PLH
PHL
OUT
IN
PACKAGES
CC
PIN NUMBER
2, 27, 30, 55
and GND pin configuration minimizes high-speed
1, 29, 56
Propagation delay
nAx to nBx
Input capacitance
Output capacitance
Total supply current
OH
, 64mA I
PARAMETER
TEMPERATURE RANGE
nBx to nAx
OL
).
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
LE1B, LE2B, LEA1B, LEA2B
OEA, OE1B, OE2B
SYMBOL
1Bn
2Bn
An
OUTSIDE NORTH AMERICA
2
74ABTH16260 DGG
74ABT16260 DGG
74ABTH16260 DL
74ABT16260 DL
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed
D-type latch used in applications where two separate data paths
must be multiplexed onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing of
address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does
not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
T
amb
Data inputs/outputs (A)
Data inputs/outputs (B1)
Data inputs/outputs (B2)
Output enable input (active low)
Latch enable inputs
V
Outputs disabled
V
I/O
CONDITIONS
= 25 C; GND = 0V
I
C = 50 pF
C
= 0 V or V
= 0 V or 5.0 V
L
= 50 pF
NORTH AMERICA
CC
BH16260 DGG
BT16260 DGG
BT16260 DL
BH16260 DL
FUNCTION
CC
74ABTH16260
through a pull-up resistor;
74ABT16260
Product specification
TYPICAL
DWG NUMBER
853-2048-18945
100
2.8
2.5
4
6
SOT371-1
SOT364-1
SOT371-1
SOT364-1
UNIT
pF
pF
ns
ns
A