SCC2698B Philips Semiconductors, SCC2698B Datasheet - Page 7

• Manufacturer Part Number: SCC2698B
• Description: Enhanced octal universal asynchronous receiver/transmitter Octal UART
• Manufacturer: Philips Semiconductors

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1. Reserved registers should never be read during normal operation since they are reserved for internal diagnostics.
2. See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681
Philips Semiconductors
clock is used instead of a crystal, X1 must be driven and X2 left
floating as shown in Figure 9. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
Table 1.
NOTE:
ACR = Auxiliary control register
CR
CSR = Clock select register
CTL
CTPL = Counter/timer preset lower register
CTU = Counter/timer upper
CTPU = Counter/timer preset upper register
MR
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 26 commonly used data
communications baud rates ranging from 50 to 115.2K baud.
Thirteen of these are available simultaneously for use by the
receiver and transmitter. Eight are fixed, and one of two sets of five
can be selected by programming ACR[7]. The clock outputs from
the BRG are at 16X the actual baud rate. The counter/timer can be
2000 Jan 31
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
A4
= Command register
= Counter/timer lower
= Mode register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Register Addressing
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
Units A and B
Units C and D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RDN=0)
MR1a, MR2a
SRa
BRG Test
RHRa
IPCRA
ISRA
CTUA
CTLA
MR1b, MR2b
SRb
1X/16X Test
RHRb
Reserved
Input port A
Start C/T A
Stop C/T A
MR1c, MR2c
SRc
Reserved
RHRc
IPCRB
ISRB
CTUB
CTLB
MR1d, MR2d
SRd
Reserved
RHRd
Reserved
Input port B
Start C/T B
Stop C/T B
2
1
1
1
1
2
WRITE
(WRN=0)
MR1a, MR2a
CSRa
CRa
THRa
ACRA
IMRA
CTPUA
CTPLA
MR1b, MR2b
CSRb
CRb
THRb
Reserved
OPCRA
Reserved
Reserved
MR1c, MR2c
CSRc
CRc
THRc
ACRB
IMRB
CTPUB
CTPLB
MR1d, MR2d
CSRd
CRd
THRd
Reserved
OPCRB
Reserved
Reserved
1
1
1
1
1
1
SR
THR = Tx holding register
RHR = Rx holding register
IPCR = Input port change register
ISR
IMR
OPCR = Output port configuration register
7
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
= Status Register
= Interrupt status register
= Interrupt mask register
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied even if the internal
BRG is not used.
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The clock
selectors allow the independent selection, by the receiver and
transmitter, of any of these baud rates or an external timing signal.
Counter–Timer
The four Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
Units G and H
Units E and F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RDN=0)
MR1e, MR2e
SRe
Reserved
RHRe
IPCRC
ISRC
CTUC
CTLC
MR1f, MR2f
SRf
Reserved
RHRf
Reserved
Input port C
Start C/T C
Stop C/T C
MR1g, MR2g
SRg
Reserved
RHRg
IPCRD
ISRD
CTUD
CTLD
MR1h, MR2h
SRh
Reserved
RHRh
Reserved
Input port D
Start C/T D
Stop C/T D
1
1
1
1
1
1
SCC2698B
Product specification
WRITE
(WRN=0)
MR1e, MR2e
CSRe
CRe
THRe
ACRC
IMRC
CTPUC
CTPLC
MR1f, MR2f
CSRf
CRf
THRf
Reserved
OPCRC
Reserved
Reserved
MR1g, MR2g
CSRg
CRg
THRg
ACRD
IMRD
CTPUD
CTPLD
MR1h, MR2h
CSRh
CRh
THRh
Reserved
OPCRD
Reserved
Reserved
1
1
1
1
1
1