SC2595 Semtech Corporation, SC2595 Datasheet - Page 6

• Manufacturer Part Number: SC2595
• Description: Integrated Linear DDR Termination Regulator
• Manufacturer: Semtech Corporation

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Overview
Overview
Overview
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfers speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V; the power dissipation is smaller than
SDRAM. For above reasons, it is very popular and widely
used in M/B, N/B, Video-cards, CD ROM drives, Disk
drives.
Regarding the DDR power management solution, there
are two topologies can be selected for system design-
ers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and the
board space needed is bigger. Another solution is linear
mode regulator, which costs less, and needs the less
board space. For two DIMM motherboards, system de-
signers usually choose the linear mode for DDR power
management solution.
Applications
T T T T T ypical Application Cir
Two different application circuits are shown below in Fig-
ure 1 to Figure 2. Each circuit is designed for specific
condition. More details are described below. See Note
1. Below for recommended power up sequencing.
Application_1: Standar
Application_1: Standar
Application_1: Standard SS
The AV
together for SSTL-2 application. It only needs a 2.5V
power rail for normal operation. System designer can
save the PCB space and reduce the cost. Please refer
to figures 3 to 4 for test waveforms.
© 2007 Semtech Corp.
Overview
Overview
Application_1: Standar
Application_1: Standar
POWER MANAGEMENT
Application Information
ypical Application Cir
ypical Application Cir
ypical Application Circuits & W
ypical Application Cir
Csence
2.2uF
CC
Cref
Figure 1: Standard SSTL-2 application
10nF
1
2
3
4
pins, the PV
NC
GND
VSENSE
VREF
SC2595
VDDQ
PVCC
AVCC
CC
VTT
pin, and the V
cuits & W
cuits & W
cuits & Wa a a a a v v v v v ef ef ef ef eforms
cuits & W
d SS
d SS
d SS
d SSTL
8
7
6
5
Cin2
1uF
TL TL
TL TL-2 Application
R1
5.1
-2 Application
-2 Application
-2 Application
-2 Application
Cin1
68uF
DDQ
2.5V
VDD
pin can be tied
orms
orms
orms
orms
Cout1
220uF
Cout2
10uF
1.25V
VTT
6
Application_2: Lower Power Loss Configuration
Application_2: Lower Power Loss Configuration
Application_2: Lower Power Loss Configuration
Application_2: Lower Power Loss Configuration
Application_2: Lower Power Loss Configuration
f f f f f or SS
If power loss is a major concern, separated the PV
the AV
operate at lower voltage (1.8V to 2.5V). If 2.5V voltage
is applied on AV
lower due to the lower operating voltage applied on the
PV
and 12.
Figure 2: Lower power loss for SSTL-2 application
Notes:
Notes:
Notes:
Notes:
Notes:
(1) Power up of AV
or SS
or SS
or SS
or SSTL
Csense
2.2uF
CC
. Please find the relative test result in Figures 5, 11
(b) If and when AV
(c) If the AV
(a) The preferred mode of operation is when the
CC
10nF
Cref
TL TL
TL TL-2 -2 -2 -2 -2
single supply.
rise simultaneously.
SDRAM.
1
2
3
4
the V
the V
V
nected in a way such that, AV
and the V
AV
up, which may cause permanent damage to the
separate to that of the V
precedes V
DDQ
NC
GND
VSENSE
VREF
CC
. This can cause the SDRAM device to latch-
, PV
SC2595
DDQ
DDQ
CC
CC
CC
supply should lead AV
supply and the AV
VDDQ
DDQ
PVCC
AVCC
, PV
and the V
and V
VTT
CC
DDQ
, PV
will be a good choice. The PV
CC
CC
supply; then V
8
7
6
5
and V
DDQ
, PV
CC
2.5V
and V
pins are tied together to a
DDQ
CC
1.8V to 2.5V
DDQ
Cddq
1uF
VDD
, but the source current is
R2
R
pins are tied to a supply
DDQ
supply pins are con
DDQ
Cin2
1uF
CC
, PV
supplies.
supply pin; then
TT
CC
PRELIMINARY
CC
, PV
Cin1
output precedes
68uF
, PV
CC
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SC2595
Vin
supply should
CC
CC
Cout1
220uF
supplies
supply or
CC
Cin2
10uF
CC
form
1.25V
can
VTT