SC28L91 Philips Semiconductors, SC28L91 Datasheet - Page 22

• Manufacturer Part Number: SC28L91
• Description: 3.3V-5.0V Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
REGISTER DESCRIPTIONS MODE REGISTERS
MR0 – Mode Register 0
Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
MR0[7]—Watchdog Control
This bit controls the receiver watchdog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6]—Rx Interrupt bit 2
Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1
sets the fill level of the FIFO that generates the receiver interrupt.
MR0[6], MR1[6] Rx Interrupt bits
Note that this control is split between MR0 and MR1. This is for
backward compatibility to legacy software of the SC2692 and
SCN2681 dual UART devices.
Table 3. Receiver FIFO
Interrupt fill level (MR0(3) = 0 (8 bytes)
Table 3a. Receiver FIFO
Interrupt fill level(MR0(3)=1 (16 bytes)
For the receiver these bits control the number of FIFO positions
filled when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
2000 Sep 22
Addr
MR0
0x00
0x08
MR0[6] MR1[6]
00
01
10
11
MR0[6] MR1[6]
00
01
10
11
3.3V–5.0V Universal Asynchronous
Receiver/Transmitter (UART)
Bit 7
Rx
WATCHDOG
0 = Disable
1 = Enable
Interrupt Condition
1 or more bytes in FIFO (Rx RDY)
6 or more bytes in FIFO
4 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
Interrupt Condition
1 or more bytes in FIFO (Rx RDY)
8 or more bytes in FIFO
12 or more bytes in FIFO
16 bytes in FIFO (Rx FULL)
BIT 6
RxINT BIT 2
See Tables in
MR0 descrip-
tion
BITS 5:4
TxINT (1:0)
See Table 4
22
BIT 3
FIFO SIZE
0 = 8 byte FIFO
1 = 16 byte FIFO
MR0[5:4]—Tx interrupt fill level.
Table 4. Transmitter FIFO
Interrupt fill level MR0(3) = 0 (8 bytes)
Table 4a. Transmitter FIFO
Interrupt fill level MR0(3) = 1 (16 bytes)
For the transmitter these bits control the number of FIFO positions
empty when the transmitter will attempt to interrupt. After the reset
the transmit FIFO has 8 bytes empty. It will then attempt to interrupt
as soon as the transmitter is enabled. The default setting of the MR0
bits [5:4] condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one–byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3]—FIFO size
Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4
MR0[2:0]—Baud Rate Group Selection
These bits are used to select one of the six–baud rate groups.
See Table 5 for the group organization.
Other combinations of MR2[2:0] should not be used.
MR0[5:4]
00
01
10
11
MR0[5:4]
00
01
10
11
000 Normal mode
001 Extended mode I
100 Extended mode II
Interrupt Condition
8 bytes empty (Tx EMPTY)
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty (Tx RDY)
Interrupt Condition
16 bytes empty (Tx EMPTY)
8 or more bytes empty
12 or more bytes empty
1 or more bytes empty (Tx RDY)
BIT 2
BAUD RATE
EXTENDED II
0 = Normal
1 = Extend II
BIT 1
TEST 2
Set to 0
Product specification
SC28L91
BIT 0
BAUD RATE
EXTENDED 1
0 = Normal
1 = Extend