SC28L92 Philips Semiconductors, SC28L92 Datasheet - Page 30

• Manufacturer Part Number: SC28L92
• Description: 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
when the CPU reads the receive FIFO, only if (after this read) there
are no more characters in the FIFO – the Rx FIFO becomes empty.
OPCR—Output Port Configuration Register
OPCR OUTPUT PORT CONFIGURATION REGISTER
OPCR[7]—OP7 Output Select
This bit programs the OP7 output to provide one of the following:
OPCR[6]—OP6 Output Select
This bit programs the OP6 output to provide one of the following:
OPCR[5]—OP5 Output Select
This bit programs the OP5 output to provide one of the following:
OPCR[4]—OP4 Output Select
This field programs the OP4 output to provide one of the following:
2000 Jan 21
0
1
0
1
0
1
0
1
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
OPCR
Addr
0x0D
The complement of OPR[7].
The Channel B transmitter interrupt output which is the
complement of ISR[4]. When in this mode OP7 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
The complement of OPR[6].
The Channel A transmitter interrupt output which is the
complement of ISR[0]. When in this mode OP6 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
The complement of OPR[5].
The Channel B receiver interrupt output which is the
complement of ISR[5]. When in this mode OP5 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
The complement of OPR[4].
The Channel A receiver interrupt output which is the
complement of ISR[1]. When in this mode OP4 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
0 = OPR[7]
1 = TxRDY B
Bit 7
OP7
0 = OPR[6]
1 = TxRDY A
BIT 6
OP6
1 = RxRDY/FFULL B
0 = OPR[5]
BIT 5
OP5
30
1 = RxRDY/FFULL A
0 = OPR[4]
SRB—Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR[3:2]—OP3 Output Select
This bit programs the OP3 output to provide one of the following:
OPCR[1:0]—OP2 Output Select
This field programs the OP2 output to provide one of the following:
00
01
10
11
00
01
10
11
BIT 4
OP4
The complement of OPR[3].
The counter/timer output, in which case OP3 acts as an
open-drain output. In the timer mode, this output is a square
wave at the programmed frequency. In the counter mode,
the output remains High until terminal count is reached, at
which time it goes Low. The output returns to the High state
when the counter is stopped by a stop counter command.
Note that this output is not masked by the contents of the
IMR.
The 1X clock for the Channel B transmitter, which is the
clock that shifts the transmitted data. If data is not being
transmitted, a free running 1X clock is output.
The 1X clock for the Channel B receiver, which is the clock
that samples the received data. If data is not being received,
a free running 1X clock is output.
The complement of OPR[2].
The 16X clock for the Channel A transmitter. This is the
clock selected by CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111.
The 1X clock for the Channel A transmitter, which is the
clock that shifts the transmitted data. If data is not being
transmitted, a free running 1X clock is output.
The 1X clock for the Channel A receiver, which is the clock
that samples the received data. If data is not being received,
a free running 1X clock is output.
BIT 3
OP3
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
BIT 2
OP2
BIT 1
OP1
00 = OPR[2]
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
Product specification
SC28L92
BIT 0
OP0