MC74HC4060ADTR2G ON Semiconductor, MC74HC4060ADTR2G Datasheet - Page 5
MC74HC4060ADTR2G
Manufacturer Part Number
MC74HC4060ADTR2G
Description
IC COUNTER 14STAGE BIN 16-TSSOP
Manufacturer
ON Semiconductor
Series
74HCr
Type
Binaryr
Datasheet
1.MC74HC4060ADR2.pdf
(14 pages)
Specifications of MC74HC4060ADTR2G
Logic Type
Binary Counter
Direction
Up
Number Of Elements
1
Number Of Bits Per Element
14
Reset
Asynchronous
Count Rate
50MHz
Trigger Type
Negative Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Technology
CMOS
Number Of Elements
1
Number Of Bits
14
Logic Family
HC
Logical Function
Counter
Operating Supply Voltage (typ)
2.5/3.3/5V
Package Type
TSSOP
Propagation Delay Time
1000ns
Operating Temp Range
-55C to 125C
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing
-
Lead Free Status / Rohs Status
Compliant
Other names
MC74HC4060ADTR2G
MC74HC4060ADTR2GOSTR
MC74HC4060ADTR2GOSTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC74HC4060ADTR2G
Manufacturer:
ON Semiconductor
Quantity:
5
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
* For T
* Used to determine the no−load dynamic power consumption: P
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
AC CHARACTERISTICS
TIMING REQUIREMENTS
Symbol
Symbol
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
t
t
C
TLH
t
C
t
THL
rec
t
t
r
, t
PD
w
w
in
f
,
V
V
Semiconductor High−Speed CMOS Data Book (DL129/D).
(DL129/D).
A
CC
CC
= 25 C and C
= 2.0 V: t
= 3.0 V: t
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)*
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width, Clock
(Figure 1)
Minimum Pulse Width, Reset
(Figure 2)
Maximum Input Rise and Fall Times
(Figure 1)
P
P
= [93.7 + 59.3 (n−1)] ns
= [61.5+ 34.4 (n−1)] ns
L
= 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
(C
(Input t
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Parameter
Parameter
r
= t
f
= 6 ns) − continued
http://onsemi.com
MC74HC4060A
V
V
CC
CC
D
= C
= 4.5 V: t
= 6.0 V: t
5
PD
V
CC
P
P
= [30.25 + 14.6 (n−1)] ns
= [24.4 + 12 (n−1)] ns
2
f + I
CC
V
CC
V
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
V
V
CC
CC
. For load considerations, see Chapter 2 of the
Typical @ 25 C, V
−55 to 25 C
−55 to 25 C
1000
100
800
500
400
75
27
15
13
10
75
20
17
75
27
15
13
75
27
15
13
Guaranteed Limit
Guaranteed Limit
35
1000
CC
85 C
85 C
125
100
800
500
400
95
32
19
16
10
25
21
95
32
19
16
95
32
19
16
= 5.0 V
125 C
125 C
1000
150
120
800
500
400
110
110
110
36
22
19
10
30
25
36
23
19
36
23
19
Unit
Unit
pF
pF
ns
ns
ns
ns
ns