L64118 LSI Logic Corporation, L64118 Datasheet
L64118
Related parts for L64118
L64118 Summary of contents
Page 1
... The L64118 supports industry-standard SDRAM memory Mbytes, using 16 and 64 Mbit SDRAMs. The SDRAM interface supports PC66/100-compliant SDRAMS. The L64118 is offered in LSI Logic’s 3.3 V G10 and is packaged in a 256-pin PBGA (IF) package. February 1999 Copyright © 1997, 1998 by LSI Logic Corporation. All rights reserved. ...
Page 2
... Mbyte x 16 The L64118’s embedded 32-bit MIPS CPU (TR4101) runs at 54 MHz. The chip’s CPU block is 32 bit, while the bus interface to external memory (through the SDRAM controller bit. The CPU can run MIPS16 and MIPS32 instructions. The 32-bit operations allow high-performance operation, while 16-bit operations allow for code optimization and memory savings ...
Page 3
... It outputs demultiplexed audio and video PES streams for processing by the L64105. This decoder’s extended channel buffer feature lets you use part of the L64118 SDRAM space to store A/V PES data directed to the L64105. One benefit of this is that it lets you free memory in the L64105 and increases its On-Screen Display (OSD) capability ...
Page 4
... The 27 MHz system clock drives the L64118 internal demultiplexer block, as well as most of the peripheral modules. The PLL block generates 54 MHz from the 27 MHz system clock to drive the CPU logic. The L64118 includes four DMA channels (one dedicated to the IEEE1284 port, three independent) that can be used to transfer data between peripheral ports and memory, from one memory location to another, or from memory to an external system device ...
Page 5
... Two interrupt handling modes: – – L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 32-bit TR4101 54 MHz TinyRISC CPU MIPS16 and MIPS-II instruction set compatible Four Kbyte Data (direct mapped) and Eight Kbyte (two-way set associative) instruction cache ...
Page 6
... Enhanced serial I/O for modem use SDRAM Controller SDRAM Controller supports 16 and 64 Mbit SDRAM devices SDRAM Controller support for Mbytes 6 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 32-bit external addressing 8-/16-/32-bit data bus width Multiplexed address/data as well as eight demultiplexed address pins ...
Page 7
... Commercial temperature range 0 C–70 C ambient Low-power, 3 10%) process Architectural Overview The components of the L64118 are integrated to provide a complete system solution for demultiplexing and processing incoming MPEG-2 Transport Stream packets. Figure 2 shows the three main blocks of the L64118: the TR4101 CPU and associated core building blocks, the transport (demultiplexer) block, and the peripheral device interfaces ...
Page 8
... Internal Peripheral Bus (PBus) Register Descrambler File Channel PID Decoder Processor Interface PCR VCx0 Clock 27 MHz Recovery 8 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Interrupt Bus Controller Controller Cache Controller Timers BBus Cache C2P ICEport CPU Block PBus DMA ...
Page 9
... TinyRISC MIPS CPU Core With its powerful MIPS CPU, the L64118 can support all of the system’s general-purpose control requirements, including: Complete set-top system initialization and testing Security handling Communication ports protocol processing Remote control handling PCR recovery and locking Audio/video synchronization for lip-syncing The CPU also supports transport and system data software processing on data posted to the SDRAM by the transport processing block ...
Page 10
... SDRAM) without requiring external glue logic. The interface between the CPU subsystem and the rest of the L64118 is implemented by the C2P unit. The C2P module translates 32-bit data accesses by the CPU to 8- and 16-bit data accesses on the Peripheral Bus, which connects all other blocks ...
Page 11
... Eight address bits are available as demultiplexed bits for easy interface to devices that do not need the full address space. In addition a demultiplexed mode can be configured to provide a 24-bit address and 16-bit data bus. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 11 ...
Page 12
... MHz output clock Peripherals The L64118 integrates several serial and parallel ports, providing a high degree of connectivity to various types of peripherals. The communication ports include: Three 8251 RS232 serial communication ports connect the set-top box to a dumb monitor, modem, or PC. The modem communicates between the subscriber and the main station, or back channel ...
Page 13
... One IEEE1284 parallel communication port for fast communication with workstation. The L64118 includes an on-chip DMA controller dedicated for data transfers between the IEEE1284 parallel communication port and the main memory. 2 One I C-compatible serial communication port to communicate with 2 devices using I C data links. This type of bus is common in video encoders, audio DACs, remote control devices, and RF tuners ...
Page 14
... Because the L64118 does not have a Memory Management Unit (MMU), kuseg addresses are mapped unchanged to physical addresses. The L64118 does not map kseg2 ; thus, kseg2 addresses cannot be used by 14 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) ...
Page 15
... PSI/PES data is stored in a noncacheable location, since they are posted by the PID processor). As part of the CPU subsystem, the L64118 a small module (the MMU Stub) that maps the kseg0 and kseg1 segments to the same physical address. It does this by clearing the three most significant bits of the address in the kseg0 and kseg1 segments presented by the CPU (on the internal CPU bus) ...
Page 16
... The address space of the L64118 is partitioned into the following areas: CPU/Peripheral This address space contains the control and status registers for the CPU and core building blocks. Configuration Register Space The space contains registers that define the configuration of each peripheral on the PBus partitioned into 1 Kbyte segments, where each segment corresponds to the Confi ...
Page 17
... N/A 0xBFE0.0000 N/A 0xBFC0.0000 0x9FC0.0000 2 0xB800.0000 0x9800.0000 4 0xB400.0000 0x9400.0000 6 0xB000.0000 0x9000.0000 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 17 PBus to EBus Address Mapping PBus Address 0x0000.0000–0x1F.FFFF 0x0100.0000–0x017F.FFFF 0x0100.0000–0x01FF.FFFF BBus Base Address Space Address Name 0x1FFF.0000 CPU/Peripheral 1 (Reserved ) 0x1FF8.0000 Not used 0x1FF4 ...
Page 18
... Same address used on the EBus and BBus when 32-bit devices are accessed. Signals This section describes the signals used by the L64118. Figure 3 shows the L64118 non-GPIO mode signals in functional groups and Figure 4 shows the L64118 GPIO mode signals. The signals are described by group ...
Page 19
... RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2 2 SCL I C-compatible SDA Port TTXDATA Teletext Port TTXREQ GPIO[49:48,46:45,43:42] General-Purpose I/Os L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 19 SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK SDQMH SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD ...
Page 20
... RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2 2 SCL I C-compatible SDA Port GPIO13 Teletext Port GPIO12 GPIO[49:48,46:45,43:42] General-Purpose I/Os 20 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK GPIO6 SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD ...
Page 21
... CSn[5]/MEMSTBn not asserted DTRn0 not asserted FAULTn/AUXSB not asserted GPIO42, 43, 45, floating 46, 48, 49 INITn/AUXPID[0] not asserted IRTX not asserted PDATA_DIR/ drives assertion OP_MODE[2] PDATA[7:0] floating RDn not asserted L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101 Notes ...
Page 22
... SCx_VPP_ENn SCx_VCC_ENn SCL SDA SDCLK SDQMH SDQML SRASn SWEn 22 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Default Values for L64118 Output and Bidirectional 1 Signals After Reset (Cont.) Default Value not asserted driving an unknown value driving an unknown value floating pull-up resistor ...
Page 23
... TXD0/2 TXD1/ICE_TX VVALID WRn 1. A few cycles after reset (RESETn is driven HIGH), the L64118 initiates a transaction on the EBus, changing some of the default values in this table. Channel Interface Port These signals provide the physical connection to Channel Interface devices, such as LSI Logic’s L64724 or L64768. This port supports both parallel and serial connections ...
Page 24
... CERRn are carrying valid data. When CVALID is asserted, a rising edge of CCLK latches the CDATA[7:0] signals into the L64118. 27 MHz System Clock This input provides the clock signal to the L64118. It must be driven by the external 27 MHz VCxO (the voltage control input is controlled by SDET and the external RC filter). ...
Page 25
... PLL stability. Multiplexed Address/Data Bus AD[31:0] is the multiplexed address/data bus. The L64118 can be programmed to drive the full address on this bus at access start. After this address phase the bus presents write data for a write or the external device drives data on the bus in a read ...
Page 26
... BEn[2] BEn[3] CPU_CLK 26 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) The byte enables always correspond to the same physical lines on the AD bus: BEn[1] corresponds to AD[15:8], BEn[0] to AD[7:0]. Byte Enable The four byte enable outputs are asserted during a read or write transaction on the EBus to control which of the four byte lanes are enabled ...
Page 27
... For self-acknowledge devices, the external EACKn pin can be ignored, so the transaction completes when the wait state generator expires. This is controlled by the XACK bit in the CECFGn register. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 27 Output Output Bidirectional Output ...
Page 28
... These general signals are not necessarily associated with a specific function or module of the L64118. OP_MODE[1:0] OP_MODE[2]/PDATA_DIR 28 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Interrupt This unmaskable interrupt can be used for highest priority system needs. Interrupts These four external interrupts can be programmed to be level- or edge-triggered sensitive ...
Page 29
... IDDTN ZTESTn Serial Port/ICEPort These signals connect the L64118 to an external modem, PC, terminal, or other host that includes an RS232 interface. The L64118 contains three serial ports that comply with the asynchronous specification of the RS232 standard. The on-chip baud rate generators support the standard bit rate for serial communication. Three of the SIO1 signals can be confi ...
Page 30
... CTSn1/ICECLK DSRn0 DTRn0 30 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) GPIO7 CTSn0 can serve as a general-purpose I/O signal (GPIO7) by setting bit 1 in the General-Purpose Mode register. Clear to Send Port1 This pin can serve as either the Clear to Send signal of SIO1 the ICEport clock input for the ICEport module. The strap option on GPIO[43] controls this pin’ ...
Page 31
... The strap option on GPIO[43] controls this pin’s functionality and usage. If GPIO[43] is sampled HIGH during reset, this pin serves as RXD1. In that case, this signal provides serial data from an external RS232 device. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 31 Input Output Bidirectional Output ...
Page 32
... TCLK TXD0 TXD1/ICE_TX 32 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) The protocol of this pin is similar to that of TxD1. The receive baud rate is determined by programming the SIO Baud Rate register. The data received on RXD1 is latched in the Receive register of Port 1. If GPIO[43] is sampled LOW during reset, then this pin serves as the receive port for the ICEport in the L64118 ...
Page 33
... The SBA[1:0] outputs support two- and four-bank SDRAM devices. The L64118 automatically performs SDRAM refreshes. The L64118 does not support the Chip Select (CSn) and Clock Enable (CKE) signals. Tie these SDRAM signals active LOW and HIGH, respectively, on the SDRAM device(s) used. ...
Page 34
... L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) SDRAM Data Bus This data bus is driven by the SDRAM during a read operation, and driven by the L64118 during a write operation 3-stated after reset and when there are no memory accesses. Column Address Strobe This signal is the active LOW column address strobe ...
Page 35
... Audio/Video Decoder Port These signals provide the interface between the L64118 and an external MPEG-2 Audio/Video decoder. This interface supports a seamless connection between the L64118 and LSI Logic’s L64105 A/V decoders. It supports a serial data transfer rate Mbits/s in serial mode, 9 Mbytes/s in parallel mode. The actual data rate is controlled by the audio and video request signals coming out from the A/V decoder device ...
Page 36
... ACLK AVDD AVSS IREF 36 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) clocked in to the external A/V decoder. Deassertion of VREQn indicates that the A/V decoder is not ready to accept video data. Video Data Valid When asserted, this signal indicates that valid video data is available on the AVD line ...
Page 37
... FSC_CNTL DCO_DIV REF_DIV IEEE 1149.1 (JTAG) Port This group of signals drive the IEEE1149.1 Test Access Port (TAP). TCK TDI TDO TMS TRSTn L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 37 IREF Connection to RC Devices AVDD 0 IREF AVSS 18 IREF 18-bit DAC ...
Page 38
... IEEE1284 Parallel Port and Auxiliary Port These signals provide a parallel connection between the L64118 and an external peripheral device. The port complies to IEEE1284 standards and supports several modes. The 1284 mode is enabled when the AUX_SEL bit is reset (System Mode register, bit 4). ...
Page 39
... INIT/AUXPID[2] 1284 - Peripheral Initialization In 1284 mode, this signal functions as INITn. When reset LOW, this signal resets the IEEE1284 port and returns the logic to the compatibility and idle state. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 39 Bidirectional Bidirectional Bidirectional Bidirectional ...
Page 40
... PDATA[7:0] PDATA_DIR/OP_MODE[2] PERROR/AUXPID[0] 40 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Aux - Packet ID [2] In Aux mode, this signal is part of a three-bit packet ID that can be assigned to PIDs that are output to the Aux port. GPIO25 This signal can also serve as a general-purpose I/O signal (GPIO25) by setting bit 3 in the General-Purpose Mode register ...
Page 41
... GPIO28 This signal can also serve as a general-purpose I/O signal (GPIO28) by setting bit 3 in the General-Purpose Mode register. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 41 Output Bidirectional Output Output Bidirectional ...
Page 42
... L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 1284 - Data Strobe In 1284 mode, this signal functions as STROBEn. When set LOW, this signal indicates that valid data is present on PDATA[7:0]. L64118 latches the data on the rising edge of STROBEn. Aux - Aux Port Direction In Aux mode, this signal is used to specify the direction of the aux port if the PINACT bit (bit 4) is set in the Aux Control register ...
Page 43
... These signals provide the connection between the L64118 and external SmartCard devices. These signals are used by the L64118 to initialize external devices in a system with such a port. The L64118 supports two independent SmartCard devices. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 43 ...
Page 44
... General-Purpose Mode register. By default, this signal floats after reset. SmartCard 0 I/O This signal transfers data (using the coupler) between SmartCard 0 and the SmartCard port of the L64118 open-drain. This signal must be pulled external resistor after reset. SmartCard 0 Reset This signal resets SmartCard 0. ...
Page 45
... When HIGH, this signal indicates that a card is inserted in slot 1. GPIO36 SC1_CLK can serve as a general-purpose I/O signal (GPIO36) by setting bit 5 in the General-Purpose Mode register. By default, this signal floats after reset. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 45 Output Bidirectional Output Bidirectional Output Bidirectional ...
Page 46
... L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) SmartCard 1 I/O This signal transfers the data (using the coupler) between SmartCard1 and the SmartCard port of the L64118 open-drain. This signal must be pulled external resistor after reset. SmartCard 1 Reset This signal resets SmartCard1. ...
Page 47
... These signals provide the connection between the L64118 and an external infrared receiver and transmitter. IRBL IRRX0 IRRX1 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 47 Infrared Blaster This signal is the infrared blaster output. This signal can be configured to reflect the value of the infrared transmitter output. ...
Page 48
... IRTX General-Purpose Pins The general-purpose I/O signals for the L64118 let you control and monitor various external events. These signals consist of eight groups. Group 7 contains dedicated GPIO signals, whereas the other groups multiplex the GPIO signals with other functions. Note that all pins within a GPIO group must be enabled or disabled as a group ...
Page 49
... TTXREQ GPIO12 TTXDATA GPIO13 Table 8 Group 4: PIO (IEEE 1284) Signals Pin Name GPIO Signal AUTOFDn GPIO14 BUSY GPIO15 PDATA[7:0] GPIO[23:16] FAULTn GPIO24 INITn GPIO25 PERROR GPIO26 SELECT GPIO27 SELECTINn GPIO28 STROBEn GPIO29 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 49 ...
Page 50
... Pin Name SC1_RSTn SC1_DETECT SC1_VCC_ENn SC1_CLK SC1_VPP_ENn Table 11 Pin Name IRRX0 IRRX1 IRTX IRBL 50 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Group 5: SmartCard 0 Signals GPIO Signal GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 Group 6: SmartCard 1 Signals GPIO Signal GPIO35 GPIO36 GPIO37 ...
Page 51
... The delay that the general-purpose module inserts in writing to an output general-purpose pin is not more than 1 s (for SCLK = 27 MHz). L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 51 Group 7: Dedicated GPIO Signals GPIO Signal GPIO[43:42] ...
Page 52
... Absolute Maximum Ratings (Table 13) Recommended Operating Conditions (Table 14) Capacitance (Table 15) DC Characteristics (Table 16) Pin Description Summary (Table 17) The following tables provide the maximum ratings, operating conditions, and capacitances for the 3.3 V, G10-p implementation of the L64118. Table 13 Symbol ...
Page 53
... Ambient Temperature A Table 15 Capacitance 1 Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C I/O Bus Capacitance IO 1. Measurement conditions are V frequency = 1 MHz. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 53 Limits Unit + 3 3 Min Typ Max 5.0 – – 5.0 – – 5.0 – ...
Page 54
... For CMOS and TLL inputs. 3. Not more than one output may be shorted at a time for a maximum duration of one second. 4. These values scale proportionally for output buffers with different drive strengths. 54 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 1 Condition I = 2.0 mA ...
Page 55
... Aux Sync Byte GPIO15 General-Purpose IO 15 CCLK Channel Data Clock CDATA[7:0] Channel Data CERRn Channel Data Error CPU_CLK EBus Clock Output CSn[3:0] EBus Chip Select L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 55 Drive 1 Type (mA) Active Output 6 LOW Output 6 HIGH Output ...
Page 56
... IDDTN Test Pin INITn/ 1284 Initialization AUXPID[2] Aux Packet ID 2 GPIO25 General-Purpose I/O 25 INTn[3:0] Interrupt INTn4 Interrupt IRBL IR Blaster GPIO47 General-Purpose I L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Drive 1 Type (mA) Active Output 6 LOW Bidirectional 6 Output 6 LOW Input – LOW ...
Page 57
... RXD0 Receive Data (SIO 0) GPIO11 General-Purpose I/O 11 RXD1/ Receive Data (SIO 1) ICE_RX Receive Data Serial ICE Port RXD2 Receive Data (SIO 2) SA[11:0] SDRAM Address Bus L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 57 Drive 1 Type (mA) Active – – Input – Bidirectional 4 Input – ...
Page 58
... General-Purpose I/O 36 SC1_I/O SmartCard 1 Data SC1_RSTn SmartCard 1 Reset GPIO35 General-Purpose I/O 35 SC1_VCC_ENn SmartCard 1 VCC Enable GPIO37 General-Purpose I/O 37 SC1_VPP_ENn SmartCard 1 VPP Enable GPIO39 General-Purpose I L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Drive 1 Type (mA) Active Output 6 Output 6 Bidirectional 6 Bidirectional 6 (open drain) Bidirectional ...
Page 59
... SWEn SDRAM Write Enable TCLK UART Transmit Clock (SIO 0) TCK JTAG Scan Clock TDI JTAG Scan In TDO JTAG Scan Out TMS JTAG Mode L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 59 Drive 1 Type (mA) Active Output 8 LOW Bidirectional 8 (open drain) Input – ...
Page 60
... If only active state (LOW or HIGH) is listed, it applies to all possible pin configurations. 3. The internal pull-up resistor value is from 50–100 k 4. The internal pull-down resistor value is from 50–100 k 60 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Drive 1 Type (mA) ...
Page 61
... Packaging and Pinouts Figure 6 shows the signal solder balls of the L64118. This diagram shows the location, ball number, and signal for each solder ball on the 256-pin Plastic Ball Grid Array (PBGA) package (package code IF). This pinout drawing is followed by: a listing of the solder balls in numerical order for the L64118 ...
Page 62
... Figure 6 L64118 256-Pin PBGA Pinout 62 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) ...
Page 63
... E3 ECLK C7 F3 CDATA[ CDATA[ GPIO46 V7 J3 GPIO49 W7 K3 SCLK Y7 L3 TCK A8 M3 TMS B8 N3 AVD[2] L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 63 Signal Solder Signal Ball AVD[0] C8 SA[7] AVALID D8 VSS VREQn U8 VSS NC V8 AD[11 AD[10] Y8 AD[9] SC0_C4 A9 SBA[1] IREF B9 SBA[0] ...
Page 64
... AVALID R3 INTn4 AVD[0] P3 IRBL AVD[1] R2 IREF AVD[2] N3 IRRX0 AVD[3] P1 IRRX1 AVD[4] M4 IRTX AVD[ AVD[ L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) Solder Signal Solder Ball Ball R19 NC U2 R20 NC V2 P18 ...
Page 65
... This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code IF. L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 65 MD98.IF ...
Page 66
... Notes 66 L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) ...
Page 67
... Notes L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 67 ...
Page 68
... Fax: 44.1344.481039 Sales Offices with Design Resource Centers LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic ...