IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 52

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

rupt indication enable.
to an unavailable condition interrupt indication enable.
on the SPI-4 egress status channel.
synchronization to in synchronization condition interrupt indication enable.
to an unavailable condition interrupt indication enable. SCLK_UN_EN should
be written as a zero if using a SPI-4 egress LVTTL status clock that is less than
one-half of the MCLK frequency. The SCLK_UN_I interrupt indication is not
usable in this case.
Module status register (0x24 in the direct ac-
cessed space)
TABLE 42 - MODULE STATUS REGISTER (0x24 IN
THE DIRECT ACCESSED SPACE)
write access, and interrupt status fields are cleared by a microprocessor write
cycle, where a logical one must be written to clear the field(s) targeted, except
for the PMON field, which can not be cleared.
only be active if the corresponding field is active in the primary interrupt status
register (Direct access register 0x2C).
rupt indication.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
SPI-34_CAPTURE
SPI-43_CAPTURE
SPI-34_INSERT
SPI-43_INSERT
PMON
Reserved
I_BUS_ERR_EN
0=Disable bus error interrupt
1=Enable bus error interrupt
SPI4_INACTIVE_TRANSFER_EN SPI-4 ingress inactive transfer inter-
0=Disable inactive transfer interrupt
1=Enable inactive transfer interrupt
DCLK_UN_EN SPI-4 ingress data clock has transitioned from available
0=Disable unavailable interrupt
1=Enable unavailable interrupt
E_DIP_ERR_EN
0=Disable DIP-2 error interrupt
1=Enable DIP-2 error interrupt
E_SYNCH_EN SPI-4 egress status channel has transitioned from out of
0=Disable synchronization interrupt
1=Enable synchronization interrupt
SCLK_UN_EN SPI-4 egress status clock has transitioned from available
0=Disable unavailable interrupt
1=Enable unavailable interrupt
The Module Status register (0x24 in the direct accessed space) has read and
The Module Status register is a secondary interrupt status register and can
SPI-34_CAPTURE
0=No capture event
1=Buffer is ready for reading by the microprocessor
Field
SPI-4 egress DIP-2 error interrupt indication enable
SPI-4 ingress bus error interrupt indication enable.
SPI-3 ingress to SPI-4 egress capture event inter-
Bits
7:5
0
1
2
3
4
Length
1
1
1
1
1
3
Initial Value
0
0
0
0
0
0
52
indication.
indication.
indication.
no effect.
Module enable register (0x28 in the direct ac-
cessed space)
TABLE 43 - MODULE ENABLE REGISTER (0x28 IN
THE DIRECT ACCESSED SPACE)
and write access.
interrupt enable.
interrupt enable.
enable.
interrupt enable.
SPI-34 CAPTURE_EN
SPI-43 CAPTURE_EN
SPI-34 INSERT_EN
SPI-43 INSERT_EN
PMON_EN
Reserved
SPI-43_CAPTURE SPI-4 ingress to SPI-3 egress capture event interrupt
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-34_INSERT SPI-3 ingress to SPI-4 egress insert event interrupt
0=No insert event
1=Buffer is ready for writing by the microprocessor
SPI-43_INSERT
0=No insert event
1=Buffer is ready for writing by the microprocessor
PMON Performance Monitor event interrupt indication. Writing to this field has
0=No PMON event
1=PMON event is ready for reading by the microprocessor
The Module Enable register (0x28 in the direct accessed space) has read
SPI-34_CAPTURE_EN
0=Disable capture interrupt
1=Enable capture interrupt
SPI-43_CAPTURE_EN
0=Disable capture interrupt
1=Enable capture interrupt
SPI-34_INSERT_EN SPI-3 ingress to SPI-4 egress insert event interrupt
0=Disable insert interrupt
1=Enable insert interrupt
SPI-43_INSERT_EN
0=Disable insert interrupt
1=Enable insert interrupt
PMON_EN
0=Disable PMON interrupt
1=Enable PMON interrupt
Field
Performance Monitor event interrupt enable.
SPI-4 ingress to SPI-3 egress insert event interrupt
SPI-4 ingress to SPI-3 egress insert event
SPI-3 ingress to SPI-4 egress capture event
SPI-4 ingress to SPI-3 egress capture event
INDUSTRIAL TEMPERATURE RANGE
Bits
7:5
0
1
2
3
4
Length
1
1
1
1
1
3
APRIL 10, 2006
Initial Value
0
0
0
0
0
0