IDTCSPUA877A Integrated Device Technology, IDTCSPUA877A Datasheet - Page 12

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IDTCSPUA877A

Manufacturer Part Number
IDTCSPUA877A
Description
1.8v Phase Locked Loop Differential 1 10 Sdram Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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TEST CIRCUIT AND SWITCHING WAVEFORMS
APPLICATION INFORMATION
NOTES:
Place all decoupling capacitors as close to the CSPUA877A pins as possible.
Use wide traces for A
Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz).
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
GND
V
DDQ
Clock Structure
CARD
CARD
VIA
#1
#2
VIA
Clock Inputs and
Outputs, OE
VDD
and AGND.
1:
20%
Recommended Filtering for the Analog and Digital Power Supplies (AV
t
SLR(I/O)
80%
BEAD
0603
# of SDRAM Loads per Clock
=
4.7uF
1206
t
V
R(I),
80%
t
R(I/O)
t
R(O)
2
4
V
20%
Input and Output Slew Rates
0.1uF
0603
12
t
SLF(I/O)
2200pF
t
0603
F(I),
Min.
Clock Loading on the PLL outputs (pF)
3
6
t
F(O)
=
V
AV
AGND
80%
CSPUA877A
DD
80%
t
COMMERCIAL TEMPERATURE RANGE
F(I/O)
DD
and V
V
V
GND
DDQ
20%
20%
DDQ
)
1
V
ID
Max.
, V
10
5
10
OD
0.1uF
0603

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