IDT71P72804 Integrated Device Technology, IDT71P72804 Datasheet

IDT71P72804

Manufacturer Part Number

IDT71P72804

Description

1.8v 1m X 18 Qdr Ii Pipelined Sram

Manufacturer

Integrated Device Technology

Datasheet

1.IDT71P72804.pdf (21 pages)

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Features

Notes

1) Represents 18 signal lines for x18, and 36 signal lines for x36

2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 2 signal lines for x18, and 4r signal lines for x36.

4) Represents 36 signal lines for x18, and 72 signal lines for x36.

Functional Block Diagram

18Mb Density (1Mx18, 512kx36)

Separate, Independent Read and Write Data Ports

Dual Echo Clock Output

2-Word Burst on all SRAM accesses

DDR (Double Data Rate) Multiplexed Address Bus

DDR (Double Data Rate) Data Buses

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

Scalable output drivers

Commercial and Industrial Temperature Ranges

1.8V Core Voltage (V

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Supports concurrent transactions

One Read and One Write request per clock cycle

Two word burst data per clock on each port

Four word transfers per clock cycle (2 word bursts

on 2 ports)

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

Output Impedance adjustable from 35 ohms to 70

ohms

BWx

(Note1)

(Note2)

(Note3)

)

DATA

LOGIC

REG

CTRL

ADD

REG

CLK

GEN

(Note2)

DATA

REG

SELECT OUTPUT CONTROL

18Mb Pipelined

QDR™II SRAM

Burst of 2

WRITE DRIVER

(Note1)

MEMORY

(Note1)

ARRAY

18M

Description

nous memories with independent, double-data-rate (DDR), read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput, with two data items passed

with each read or write. Four data word transfers occur per clock

cycle, providing quad-data-rate (QDR) performance. Comparing this

with standard SRAM common I/O (CIO), single data rate (SDR) de-

vices, a four to one increase in data access is achieved at equivalent

clock speeds. Considering that QDRII allows clock speeds in excess of

standard SRAM devices, the throughput can be increased well beyond

four to one in most applications.

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

and write addresses. All read addresses are received on the first half of

the clock cycle and all write addresses are received on the second half

of the clock cycle. The read and write enables are received on the first

half of the clock cycle. The byte and nibble write signals are received on

both halves of the clock cycle simultaneously with the data they are

controlling on the data input bus.

The IDT QDRII

Using independent ports for read and write data access, simplifies

The QDRII has a single DDR address bus with multiplexed read

(Note4)

6109 drw 16

Burst of two SRAMs are high-speed synchro-

(Note1)

IDT71P72804

IDT71P72604

APRIL 2006

DSC-6109/0A

Related parts for IDT71P72804

IDT71P72804 Summary of contents

Page 1

... DATA (Note1) REG WRITE DRIVER ADD (Note2) REG (Note4) 18M MEMORY ARRAY CLK GEN SELECT OUTPUT CONTROL 1 IDT71P72804 IDT71P72604 TM Burst of two SRAMs are high-speed synchro- (Note4) (Note1 6109 drw 16 APRIL 2006 DSC-6109/0A ...

Page 2

Mb QDR II SRAM Burst of 2 The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching ...

Page 3

Mb QDR II SRAM Burst of 2 Pin Definitions Symbol Pin Function Data input signals, sampled on the rising edge of K and K clocks during valid write operations Input D[X:0] ...

Page 4

Mb QDR II SRAM Burst of 2 Pin Definitions continued Symbol Pin Function DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings ...

Page 5

... Mb QDR II SRAM Burst of 2 Pin Configuration IDT71P72804 ( Doff V REF ...

Page 6

Mb QDR II SRAM Burst of 2 Pin Configuration IDT71P72604 (512K x 36 NC ...

Page 7

Mb QDR II SRAM Burst of 2 Absolute Maximum Ratings Symbol Rating V Supply Voltage on V with TERM DD Respect to GND V Supply Voltage on V with TERM DDQ ...

Page 8

Mb QDR II SRAM Burst of 2 Application Example Data In Data Out Address MEMORY CONTROLLER ...

Page 9

Mb QDR II SRAM Burst Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Input Leakage Current I IL Output Leakage Current I OL Operating ...

Page 10

Mb QDR II SRAM Burst of 2 Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (V = 1.8 ± 100mV 1.4V to 1.9V) DD DDQ Parameter ...

Page 11

Mb QDR II SRAM Burst Test Conditions (1) Parameter Symbol Core Power Supply Voltage V DD I/O Power Supply Voltage V DDQ Input High Level V IH Input ...

Page 12

Mb QDR II SRAM Burst Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges) Symbol Parameter Clock Parameters t Clock ...

Page 13

Mb QDR II SRAM Burst of 2 Timing Waveform of Combined Read and Write Cycles Read A0 Write A1 Read tKHKL tKLKH K R tIVKH tKHIX ...

Page 14

Mb QDR II SRAM Burst of 2 IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Ac- cess Port (TAP). The package pads ...

Page 15

Mb QDR II SRAM Burst of 2 Scan Register Definition Part Instruction Register 512Kx36 3 bits 1Mx18 3 bits Identification Register Definitions INSTRUCTION FIELD ALL DEVICES Revision Number (31:29) 0x0284 Device ...

Page 16

Mb QDR II SRAM Burst of 2 Boundary Scan Exit Order ORDER PIN ...

Page 17

Mb QDR II SRAM Burst of 2 JTAG DC Operating Conditions Parameter Symbol I/O Power Supply V DDQ Power Supply Voltage V DD Input High Level V IH Input Low Level ...

Page 18

Mb QDR II SRAM Burst of 2 JTAG AC Characteristics Parameter Symbol Min TCK Cycle Time t 50 CHCH TCK High Pulse Width t 20 CHCL TCK Low Pulse Width t ...

Page 19

Mb QDR II SRAM Burst of 2 Package Diagram Outline for 165-Ball Fine Pitch Grid Array Commercial and IndustrialTemperature Range 6.42 19 ...

Page 20

... Industrial (- + Restricted Hazardous Substance Device BQ 165 Fine Pitch Ball Grid Array (fBGA) 250 (1,2) Clock Frequency in MegaHertz 200 167 IDT71P72804 QDR II SRAM Burst of 2 IDT71P72604 512K x 36 QDR II SRAM Burst of 2 6109 drw 15 for Tech Support: sramhelp@idt.com 408-284-4532 ...

Page 21

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 ( -Bit) 71P72604 (512K x 36-Bit QDR II SRAM Burst of 2 Revision History REVISION DATE PAGES 0 07/20/05 p.1-22 A 04/21/06 p.1-3,7-9 12,15,20 p. 7,11,17 ...

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