IDT72V291 Integrated Device Technology, IDT72V291 Datasheet - Page 17

• Manufacturer Part Number: IDT72V291
• Description: 128k X 9 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. LD = HIGH.
3. First data word latency: 60ns + t
Q
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
D
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
WCLK
RCLK
0
0
Q
WEN
D
of WCLK and the rising edge of RCLK is less than t
REN
edge of the RCLK and the rising edge of the WCLK is less than t
- Q
SKEW3
- D
SKEW1
WCLK
0
0
OE
RCLK
EF
WEN
REN
- D
- Q
n
n
FF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
OLZ
t
ENH
t
SKEW1
t
REF
t
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
A
t
OE
REF
(1)
+ 1*T
t
SKEW3
t
ENS
t
ENH
t
DS
RCLK
t
D
(1)
A
0
1
.
NO OPERATION
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO WRITE
t
t
DHS
ENH
SKEW3
LAST WORD
1
, then EF deassertion may be delayed one extra RCLK cycle.
TM
2
SKEW1
t
WFF
, then the FF deassertion may be delayed one extra WCLK cycle.
t
OHZ
t
t
DS
t
ENS
DS
t
CLKH
D
1
D
NO OPERATION
X
t
t
WFF
t
ENH
DH
17
DATA READ
t
t
DH
CLK
2
t
t
CLKL
CLKH
t
REF
t
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
LAST WORD
ENH
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
REF
WFF
2
). If the time between the rising edge
). If the time between the rising
TEMPERATURE RANGES
NEXT DATA READ
t
ENS
t
WFF
t
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4513 drw 10
t
DH
t
WFF
4513 drw 11
D
1