IDT88P8342 Integrated Device Technology, IDT88P8342 Datasheet - Page 4

• Manufacturer Part Number: IDT88P8342
• Description: Spi Exchange 2 X Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

EXTERNAL INTERFACES
3 interfaces, one SPI-4 interface, a serial or parallel microprocessor interface,
a JTAG interface, and a set of GPIO pins. Each of the interfaces is defined in the
relevant standard.
supported from the relevant standards, and a description of additional features
implemented to enhance the usability of these interfaces for the system architect.
SPI-3
SPI-4
full details of the implementation agreement.
IDT88P8342
SPI EXCHANGE 2 x SPI-3 TO SPI-4
The external interfaces provided on the IDT88P8342 device are two SPI-
The following information contains a set of the highlights of the features
Refer to OIF SPI-3 document for full details of the implementation agreement.
- Two instantiations of SPI-3 interface; each interface independently
- Device supports a 8-bit and 32-bit data bus structure.
- Clock rate is minimum 19.44 - to maximum 133 MHz
- Link, single port PHY and multi port PHY modes supported
- Master and slave modes supported
- Byte level and packet level transfer control mechanisms supported
- Address range 0 – 255 with support for 64 simultaneously active logical ports
- Fragment length (section) configurable from 16 – 256 bytes in 16 byte
- Configurable standard and non-standard bit and byte ordering
Refer to OIF SPI-4 phase 2 (OIF-SPI4-02.0) implementation agreement for
- One instantiation of SPI-4 interface
- Clock rate is 80 - 400 MHz (160 — 800MHz DDR)
- Link and PHY modes supported
- Address range 0 – 255 with support for 128 simultaneously active logical
multiples
configurable
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ports
4 DTPA signals supported, mapped to LP addresses 0 – 3
8 ADR signals supported
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MICROPROCESSOR INTERFACE
JTAG
GPIO
as an input or an output pin.
as possible. The following can be defined per GPIO pin:
configurable / status memory map – i.e. data memory is not required)
address)
- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples
- 256 entry calendar
- LVTTL and LVDS status signals supported
- Parallel microprocessor interface
- Serial microprocessor interface
Complies with IEEE 1149.1 standard.
Five GPIO signals are provided. Each signal may be independently defined
The GPIO signals are implemented to leave the use of the GPIO pins as flexible
- Direction (1 bit per GPIO, options are In or Out)
- Address of bit to be written / read (N bits per GPIO, includes whole
- Value to read / write (5 bits – used when address in previous register is this
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8 bit data bus for parallel operation
Byte access
Direct accessed space
Indirect access space is used for most registers
Read operations to a reserved address or reserved bit fields return 0.
Write operations to reserved addresses or bit fields are ignored.
Compliance to Motorola serial processor interface (SPI) specification
Byte access
Direct accessed space directly
Indirect access space is accessed by an indirect access scheme
Read operations to a reserved address or reserved bit fields return 0.
Write operations to reserved addresses or bit fields are ignored.
TEMPERATURE RANGE
MAY 24, 2004
INDUSTRIAL