MC74HC4040ADG ON Semiconductor, MC74HC4040ADG Datasheet
MC74HC4040ADG
Specifications of MC74HC4040ADG
MC74HC4040ADGOS
Related parts for MC74HC4040ADG
MC74HC4040ADG Summary of contents
Page 1
... Chip Complexity: 398 FETs or 99.5 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 March, 2010 − Rev. 6 http://onsemi.com PDIP− ...
Page 2
... Pin Reset Pin 8 = GND Figure 1. Logic Diagram ORDERING INFORMATION Device MC74HC4040AN MC74HC4040ANG MC74HC4040AD MC74HC4040ADG MC74HC4040ADR2 MC74HC4040ADR2G MC74HC4040ADTR2 MC74HC4040ADTR2G MC74HC4040AF MC74HC4040AFG MC74HC4040AFEL MC74HC4040AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb− ...
Page 3
MAXIMUM RATINGS Symbol Parameter V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) out I DC Input Current, per Pin Output Current, per ...
Page 4
DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Symbol Parameter Parameter I Maximum Input Leakage Current in I Maximum Quiescent Supply CC Current (per Package) AC CHARACTERISTICS ( pF, Input t L Symbol f Maximum Clock Frequency (50% Duty ...
Page 5
TIMING REQUIREMENTS (Input Symbol t Minimum Recovery Time, Reset Inactive to Clock rec (Figure 2) t Minimum Pulse Width, Clock w (Figure 1) t Minimum Pulse Width, Reset w (Figure Maximum Input ...
Page 6
Qn 50% t PLH Qn+1 50% Figure Clock Reset Q4 = Pin Pin Pin 2 SWITCHING WAVEFORMS (continued GND t PHL Q2 Q3 ...
Page 7
Clock Reset Q10 Q11 Q12 Time−Base Generator A 60Hz sinewave obtained through a 100 K resistor connected to a 120 Vac power line through a step down transformer ...
Page 8
−T− 0.25 (0.010 PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T L SEATING PLANE http://onsemi.com 8 NOTES: 1. ...
Page 9
... G K −T− SEATING PLANE 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −B− 0.25 (0.010 SOLDERING FOOTPRINT ...
Page 10
... −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE Ç ...
Page 11
... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...