IDT70V27 Integrated Device Technology, IDT70V27 Datasheet - Page 17

• Manufacturer Part Number: IDT70V27
• Description: 32k X 16 3.3v Dual-port Ram
• Manufacturer: Integrated Device Technology

Truth Table VI — Example of Semaphore Procurement Sequence
Truth Table V — Address BUSY Arbritration
NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
4. Refer to Chip Enable Truth Table.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27.
2. There are eight semaphore flags written to via I/O
Functional Description
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70V27 has an automatic power down feature
controlled by CE
down circuitry that permits the respective port to go into a standby mode
when not selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
or message center) is assigned to each port. The left port interrupt flag
(INT
(HEX), where a write is defined as CE
IV. The left port clears the interrupt through access of address location
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
X
X
H
L
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
and enable inputs of this port. If t
when BUSY
The IDT70V27 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
L
L
) is asserted when the right port writes to memory location 7FFE
CE
X
X
H
L
R
Inputs
L
R
and BUSY
Functions
outputs are driving LOW regardless of actual logic level on the pin.
0
NO MATCH
A
and CE
A
MATCH
MATCH
MATCH
0R
0L
-A
-A
14L
14R
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V27 are
1
. The CE
BUSY
APS
(2)
H
H
H
0
is not met, either BUSY
and CE
L
R
Outputs
(1)
= R/W
BUSY
1
D0 - D15 Left
R
control the on-chip power
(2)
H
H
H
= V
0
R
(1)
and read from all the I/O's (I/O
IL
L
1
1
1
1
1
1
1
0
0
0
0
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
per the Truth Table
Write Inhibit
L
Function
or BUSY
Normal
Normal
Normal
D
3603 tbl 17
0
(3)
- D
R
= LOW will result. BUSY
15
1
1
1
1
1
1
1
1
0
0
0
Right
17
7FFE when CE
port interrupt flag (INT
location 7FFF (HEX) and to clear the interrupt flag (INT
right port must read the memory location 7FFF. The message (16 bits) at
7FFE or 7FFF is user-defined since it is an addressable SRAM location.
If the interrupt func-tion is not used, address locations 7FFE and 7FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table IV for the interrupt operation.
Busy Logic
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
0
-I/O
Busy Logic provides a hardware indication that both ports of the RAM
Semaphore free
No change. Right side has no write access to semaphore
Left port obtains semaphore token
Right port has semaphore token
Semaphore free
Left port has semaphore token
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Semaphore free
Left port has semaphore token
Semaphore free
15
). These eight semaphores are addressed by A
(4)
Commercial and Industrial Temperature Range
L
L
and BUSY
= OE
L
R
) is asserted when the left port writes to memory
= V
R
IL
outputs can not be LOW simultaneously.
, R/W is a "don't care". Likewise, the right
Status
0
- A
(1,2)
2
.
3603 tbl 18
R
), the