IDT72V8985 Integrated Device Technology, IDT72V8985 Datasheet - Page 3
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IDT72V8985
Manufacturer Part Number
IDT72V8985
Description
3.3 Volt Time Slot Interchange Digital Switch 256 X 256
Manufacturer
Integrated Device Technology
Datasheet
1.IDT72V8985.pdf
(14 pages)
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PIN DESCRIPTIONS
SYMBOL
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
GND
V
DTA
RX0-7
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-7
ODE
CCO
RESET
CC
Ground.
V
Data Acknowledgment
(Open Drain)
RX Input 0 to 7
Frame Pulse
Clock
Address 0 to 5
Data Strobe
Read/Write
Chip Select
Data Bus 0 to 7
TX Outputs 0 to 7
(Three-state Outputs)
Output Drive Enable
Control Channel Output
Device Reset
(Schmitt Trigger Input)
CC
NAME
I/O
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
O
O
O
I
I
I
I
I
I
I
I
I
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
Active LOW input enabling a microprocessor read or write of control register or internal memories.
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
Ground Rail.
+3.3 Volt Power Supply.
output.
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT72V8985 internal registers.
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Connection Memory LOW and data memory.
HIGH, each channel may still be put into high-impedance by software control.
This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters,
registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
3
®
and
DESCRIPTION
GCI.
Commercial Temperature Range