SI591 Silicon Laboratories, SI591 Datasheet - Page 3

• Manufacturer Part Number: SI591
• Description: (SI590 / SI591) 1 ps MAX JITTER CRYSTAL OSCILLATOR
• Manufacturer: Silicon Laboratories

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Table 3. CLK± Output Levels and Symmetry
Table 4. CLK± Output Phase Jitter
Table 5. CLK± Output Period Jitter
LVPECL Output Option
LVDS Output Option
CML Output Option
CMOS Output Option
Rise/Fall time (20/80%)
Symmetry (duty cycle)
Notes:
Phase Jitter (RMS)
for 50 MHz < F
(LVPECL/LVDS/CML)
Phase Jitter (RMS)
for 50 MHz < F
(CMOS)
Notes:
Period Jitter*
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
1. 50  to V
2. R
3. C
1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.
2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment.
3.3 V supply voltage option only.
Parameter
term
L
= 15 pF. Sinking or sourcing 12 mA for V
Parameter
= 100  (differential).
DD
OUT
OUT
– 2.0 V.
1
2
Parameter
2
< 525 MHz
< 160 MHz
2
3
1
Symbol
SYM
t
V
V
V
V
V
V
R,
V
V
V
OD
OD
OD
OH
SE
OL
O
O
O
t
F
Symbol
J
PER
LVPECL:
LVDS:
CMOS:
CMOS with C
swing (single-ended)
LVPECL/LVDS/CML
Test Condition
DD
Preliminary Rev. 0.25
swing (diff)
swing (diff)
swing (diff)
= 3.3 V, 6 mA for V
mid-level
mid-level
mid-level
V
1.25 V (diff)
V
Symbol
Test Condition
DD
DD
Peak-to-Peak


/2
– 1.3 V (diff)
J
J
L
RMS
= 15 pF
12 kHz to 20 MHz
12 kHz to 20 MHz
Test Condition
DD
= 2.5 V, 3 mA for V
V
0.8 x V
DD
1.125
0.55
0.70
Min
1.1
0.5
45
—
—
—
—
– 1.42
DD
Min
—
—
V
DD
Min
—
—
0.95
1.20
Typ
DD
0.7
—
—
—
—
—
—
—
– 0.75
2
= 1.8 V.
Typ
—
—
Si590/591
Typ
0.5
0.6
V
DD
1.275
Max
0.95
1.20
V
350
1.9
0.9
0.4
55
—
—
– 1.25
Max
DD
35
Max
3
1.0
1.0
Units
Units
Units
V
V
V
V
ps
ns
%
ps
ps
ps
V
V
V
V
PP
PP
PP
PP
3
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