74F169SC Fairchild Semiconductor, 74F169SC Datasheet - Page 2

• Manufacturer Part Number: 74F169SC
• Description: IC COUNTER BIDIR SYNC 4ST 16SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F169SC

• Logic Type: Binary Counter
• Direction: Up, Down
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Count Rate: 90MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Timing: -

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Unit Loading/Fan Out
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable
2. Up: (74F169): TC
3. Down: TC
CEP
CET
CP
P
PE
U/D
Q
TC
0
0
Q
Pin Names
–P
–Q
0
0
–P
3
• Q
CEP • CET • PE
3
3
1
Q
inputs enters the flip-flops on the
• Q
0
• Q
2
• Q
1
• Q
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
3
• (Down) • CET
2
• Q
3
• (Up) • CET
Description
2
Mode Select Table
H
L
X
State Diagram
LOW Voltage Level
HIGH Voltage Level
Immaterial
PE CEP CET U/D
H
H
H
H
L
X
H
X
L
L
HIGH/LOW
50/33.3
50/33.3
X
X
H
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
L
L
U.L.
H
X
L
X
X
Load (P
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
Output I
20 A/ 0.6 mA
20 A/ 1.2 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
Input I
1 mA/20 mA
1 mA/20 mA
Action on Rising
n
Clock Edge
IH
OH
Q
/I
n
/I
IL
)
OL