MCP6043T Microchip Technology, MCP6043T Datasheet - Page 12

• Manufacturer Part Number: MCP6043T
• Description: 600 nA, Rail-to-Rail Input/Output Op Amps
• Manufacturer: Microchip Technology

MCP6041/2/3/4
macro model and bench testing to adjust R
frequency response peaking is reasonable. Use the
smallest reasonable value.
FIGURE 3-2:
capacitive loads.
3.6
The MCP6043 is a single amplifier with a chip select
(CS) option. When CS is pulled high, the supply current
drops to 20 pA (typ) and goes through the CS pin to
V
impedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier will
not operate properly. Figure 3-3 shows the output volt-
age and supply current response to a CS pulse.
FIGURE 3-3:
function on the MCP6043 op amp.
3.7
Good PC board layout techniques will help you achieve
the performance shown in the specs and Typical Per-
formance Curves. It will also assist in minimizing Elec-
tro-Magnetic Compatibility (EMC) issues.
3.7.1
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace to trace need to be considered.
DS21669B-page 12
SS
I
V
I
CS
VSS
I
VDD
CS
V
OUT
. When this happens, the amplifier is put into a high
IN
5 pA, typ
20 pA, typ
5 pA, typ
The MCP6043 Chip Select (CS)
Option
Layout Considerations
Hi-Z
SURFACE LEAKAGE
MCP604X
V
IL
t
ON
Amplifier circuit for heavy
Timing Diagram for the CS
0.6 µA, typ
0.6 µA, typ
R
ISO
C
L
V
IH
t
OFF
5 pA, typ
ISO
5 pA, typ
20 pA, typ
Hi-Z
until the
V
OUT
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 10
to flow; this is greater than the input current of the
MCP6041/2/3/4 family at 25°C (1 pA, typ).
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace. Figure 3-4 shows an example of
a typical layout.
FIGURE 3-4:
layout.
Circuit schematics for different guard ring implementa-
tions are shown in Figure 3-5. Figure 3-5A biases the
guard ring to the input common mode voltage, which is
most effective for non-inverting gains, including unity
gain. Figure 3-5B biases the guard ring to a reference
voltage (V
inverting gains and precision photo sensing circuits.
FIGURE 3-5:
connection strategies to reduce surface leakage
effects.
Figure 3-5A
Figure 3-5B
12
V
REF
. A 5 V difference would cause 5 pA of current
Guard Ring
REF
V
, which can be ground). This is useful for
REF
IN-
Example of Guard Ring
Two possible guard ring
2002 Microchip Technology Inc.
MCP604X
MCP604X
IN+
V
V
DD
DD
V
SS