NCP347 ON Semiconductor, NCP347 Datasheet - Page 10

• Manufacturer Part Number: NCP347
• Description: Positive Overvoltage Protection Controller
• Manufacturer: ON Semiconductor

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Undervoltage Lockout (UVLO)
device has a built-in undervoltage lockout (UVLO) circuit.
During V
disconnected from input until V
plus hysteresis, nominal. The FLAG output is tied to low as
long as V
a 60 mV hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. (See Selection Guide on page
12) Contact your ON Semiconductor representative for
availability.
Overvoltage Lockout (OVLO)
overvoltage, the device has a built-in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
5.675 V typical (NCP347MTAE). Additional OVLO
thresholds ranging from OVLO can be manufactured. (See
Selection Guide on page 12) Contact your ON
Semiconductor representative for availability.
This circuit has a 90 mV hysteresis to provide noise
immunity to transient
FLAG Output
external systems that a fault has occurred.
exceeded or when the V
threshold. When V
FLAG is held high, keeping in mind that an additional
50 ms delay has been added between available output and
FLAG = high. The pin is an open drain output, thus a pull
up resistor (typically 1 MW, minimum 10 kW) must be
added to V
FLAG level will always reflects V
device is turned off (EN = 1).
EN Input
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the R
on V
To ensure proper operation under any conditions, the
To protect connected systems on V
FLAG output is tied to low until V
The NCP347 provides a FLAG output, which alerts
This pin is tied to low as soon the OVLO threshold is
To enable normal operation, the EN pin shall be forced
The NCP347 includes an internal Low R
out
DS(on)
pin.
in
in
, during normal operation, will create low losses
does not reach UVLO threshold. This circuit has
bat
positive going slope, the output remains
. Minimum V
in
conditions.
level recovers normal condition,
in
bat
level is below the UVLO
supply must be 2.5 V. The
in
voltage is below 2.92 V,
in
in
is higher than OVLO.
status, even if the
out
DS(on)
pin from
NMOS
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NCP347
10
As example: R
Typical R
V
NMOS losses = R
ESD Tests
1.0 mF (minimum) must be connected between V
GND, close to the device.
protected input. In Contact condition, V
ESD protected input.
electrostatic discharge waveform.
PCB Recommendations
and the PCB rules must be respected to properly evacuate
the heat out of the silicon. The PAD1 is internally isolated
from the active silicon and should preferably be connected
to ground. The PAD2 of the NCP347 package is connected
to the internal NMOS drain and can be used to increase the
heat transfer if necessary from an applications standpoint.
one can either use the PCB tracks connected to Pins 4 and
5 to evacuate heat, or make profit of the PAD2 area to add
extra copper surface to reduce the junction temperature
(See Figure 20). Of course, in any case, this pad shall be not
connected to any other potential. Figure 20 shows copper
area according to R
transfer plane connected to PAD2.
out
The NCP347 input pin fully supports the IEC61000-4-2.
That means, in Air condition, V
Please refer to Figure 19 to see the IEC 61000-4-2
The NCP347 integrates a 2 amperes rated NMOS FET,
Depending upon the power dissipated in the application,
= 8 x 0.618 = 4.95 V
Figure 19. Electrostatic Discharge Waveform
DS(on)
load
= 65 mW, I
DS(on)
= 8.0 W, V
qJA
x Iout
and allows the design of the heat
out
in
2
= 618 mA
= 0.065 x 0.618
= 5.0 V
in
has a "15 kV ESD
in
has "8.0 kV
2
= 25 mW
in
and