NCP4303B ON Semiconductor, NCP4303B Datasheet - Page 17

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NCP4303B

Manufacturer Part Number
NCP4303B
Description
Secondary Side Synchronous Rectification Driver
Manufacturer
ON Semiconductor
Datasheet

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Trigger/Disable input
exhibits a typically of 12 ns delay from its activation to the
turn−off of the SR MOSFET. The main purpose of this input
is to turn−off the SR MOSFET in applications operating in
CCM mode via a signal coming from the primary side. The
primary trigger signal rising edge should come to the trigger
input before the secondary voltage reverses. Thus the driver
signal for primary switch should be delayed – refer to figure
46 for one possible method of delaying the primary driving
signal in CCM flyback topology. The trigger signal is
The NCP4303 features an ultrafast trigger input that
Figure 38. Recommended Layout When Parasitic
Inductance Compensation is Used
Figure 40. Trigger Input Internal Connection
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NCP4303A/B
17
disabled from the end of the minimum off time period to the
end of the minimum on time period. This technique is used
to:
a) Overcome false turn−off of the gate driver in case the
synchronization pulse is too wide and comes twice per
switching period (in HB and HB LLC applications).
b) Increase trigger input noise immunity against the parasitic
ringing that is present in the SMPS layout during the turn on
process.
Figure 39. Recommended Layout When Parasitic
Inductance Compensation is Not Used
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