MC33910 Freescale Semiconductor, MC33910 Datasheet - Page 37

• Manufacturer Part Number: MC33910
• Description: LIN System Basis Chip
• Manufacturer: Freescale Semiconductor

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CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see page 38).
when entering in Stop or Sleep Mode. Otherwise a timed
wake-up is performed after the period shown in
Table 21. Cyclic Sense Interval
Watchdog Status Register
is also returned when writing to the TIMCR.
WDTO - Watchdog Time Out
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
WDTO bit.
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
CYSX8
56.
This write-only bits selects the interval for the wake-up
This option is only active if the high side switch is enabled
This register returns the watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the TIMCR will clear the
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
(56)
bit CYSX8 is located in configuration register (CFR)
Table 22. Watchdog Status Register - $A/$B
Read
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
CYST1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No Cyclic Sense
WDWO
Interval
1120ms
S0
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
Table
20ms
40ms
60ms
80ms
21.
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal Mode out of Reset. This might be necessary for
analog input. Voltage is internally clamped to VDD.
WDERR - Watchdog Error
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
WDOFF - Watchdog Off
software debugging and for programming the Flash memory.
WDWO - Watchdog Window Open
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
Analog Multiplexer Control Register - MUXCR
the divider ration for the L1 input divider.
L1DS - L1 Analog Input Divider Select
1 = Last reset caused by watchdog timeout
0 = None
This read-only bit signals the detection of a missing
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
This read-only bit signals that the watchdog pin connected
1 = Watchdog is disabled
0 = Watchdog is enabled
This read-only bit signals when the watchdog window is
1 = Watchdog window open
0 = Watchdog window closed
This register controls the analog multiplexer and selects
This write-only bit selects the resistor divider for the L1
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Table 23. Analog Multiplexer Control Register -$C
Condition
Reset
Value
Reset
Write
L1DS
POR
C3
1
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATIONS
POR, Reset Mode or ext_reset
MX2
C2
0
MX1
C1
0
MX0
C0
0
33910
37