74AHC74 Philips Semiconductors, 74AHC74 Datasheet - Page 2

• Manufacturer Part Number: 74AHC74
• Description: Dual D-type flip-flop with set and reset; positive-edge trigger
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FEATURES
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (S
reset (R
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
1999 Sep 23
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Balanced propagation delays
Inputs accepts voltages higher than
V
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Output capability: standard
I
Specified from
Dual D-type flip-flop with set and reset;
positive-edge trigger
CC
40 to +85 and +125 C.
CC
category: flip-flops
D
) inputs; also
D
) and
Notes
1. C
2. The condition is V
FUNCTION TABLES
Table 1 See note 1
Table 2 See note 1
Note to Tables 1 and 2
1. H = HIGH voltage level;
QUICK REFERENCE DATA
GND = 0 V; T
t
f
C
C
SYMBOL
PHL
max
I
PD
P
f
C
V
L = LOW voltage level;
X = don’t care;
Q
nS
nS
i
/t
D
CC
PD
= input frequency in MHz; f
L
H
H
H
n+1
L
L
PLH
= LOW-to-HIGH CP transition;
(C
= output load capacitance in pF;
= C
D
D
is used to determine the dynamic power dissipation (P
L
= supply voltage in Volts.
= state after the next LOW-to-HIGH CP transition.
PD
V
propagation delay
max. clock frequency
input capacitance
power dissipation
capacitance
amb
CC
nCP to nQ, nQ
nS
V
2
PARAMETER
CC
nR
nR
= 25 C; t
D
2
, nR
H
H
H
L
L
f
2
o
D
D
) = sum of outputs;
I
INPUT
INPUT
D
= GND to V
f
i
to nQ, nQ
+
r
= t
(C
nCP
nCP
f
L
X
X
X
o
3.0 ns.
= output frequency in MHz;
CC
V
CC
C
V
V
C
f = 1 MHz;
notes 1 and 2
.
CONDITIONS
CC
I
L
L
2
= V
= 15 pF;
= 50 pF;
= 5 V
74AHC74; 74AHCT74
f
CC
o
) where:
nD
nD
X
X
X
H
L
or GND 4.0
Product specification
3.7
3.7
130
12
AHC AHCT
nQ
nQ
TYPICAL
H
H
H
L
L
n+1
OUTPUT
OUTPUT
3.3
3.7
100
4.0
16
D
in W).
nQ
nQ
ns
ns
MHz
pF
pF
H
H
H
L
L
UNIT
n+1