74AUP1G3208 Philips Semiconductors, 74AUP1G3208 Datasheet
74AUP1G3208
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74AUP1G3208 Summary of contents
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... OFF the device when it is powered down. The 74AUP1G3208 provides the Boolean function the logic functions OR, AND and OR-AND. All inputs can be connected Features Wide supply voltage range from 0 3.6 V ...
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... GND 001aad500 Fig 2. Pin configuration SOT363 (SC-88) 74AUP1G3208_1 Product data sheet Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 Marking code ...
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... Figure see Figure 5 see Figure 7 C see Figure 001aad502 Fig 6. 2-input AND gate Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate Output and Figure ...
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... V < Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate 001aad505 C Min ...
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... 1 2 3 2 4 Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate Min Max Unit 0 +125 C 0 200 ns/V Min Typ Max Unit 0.70 V ...
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... 2 4 GND Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate Min Typ Max Unit - - ...
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... 3 0 GND Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate Min Typ Max Unit - - ...
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... Figure 1.3 V 3 1.6 V 2 1.95 V 2 2.7 V 2 3.6 V 1.9 [2] Figure 1.3 V 3 1.6 V 3 1.95 V 3 2.7 V 2 3.6 V 2.6 Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate 10 +125 C [1] Typ Max Min Max Max (85 C) (125 C) 18 5.4 10.6 2.2 10.9 11.1 3.8 6.4 1.8 6.9 3.1 5.1 1 ...
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... where GND t PHL PLH Table 10. Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate 10 +125 C [1] Typ Max Min Max Max (85 C) (125 3.6 - ...
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... PULSE DUT GENERATOR [ for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate 3 EXT 001aac521 of the pulse generator ...
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... scale 2.2 1.35 2.2 0.45 1.3 0.65 1.8 1.15 2.0 0.15 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate detail 0.25 0.2 0.2 0.1 0.15 EUROPEAN ISSUE DATE PROJECTION 04-11-08 06-03-16 © NXP B.V. 2006. All rights reserved. SOT363 ...
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... Product data sheet scale 0.35 0.40 0.6 0.5 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate SOT886 4 ( EUROPEAN ISSUE DATE PROJECTION 04-07-15 04-07-22 © NXP B.V. 2006. All rights reserved ...
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... Product data sheet scale 0.35 0.40 0.55 0.35 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate SOT891 2 mm EUROPEAN ISSUE DATE PROJECTION 05-03-11 05-04-06 © NXP B.V. 2006. All rights reserved ...
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... Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date 74AUP1G3208_1 20061129 74AUP1G3208_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate Supersedes - © NXP B.V. 2006. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 29 November 2006 74AUP1G3208 Low-power 3-input OR-AND gate © NXP B.V. 2006. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 November 2006 Document identifier: 74AUP1G3208_1 All rights reserved. ...