LM4549 National Semiconductor, LM4549 Datasheet - Page 12

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LM4549

Manufacturer Part Number
LM4549
Description
AC 97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound
Manufacturer
National Semiconductor
Datasheet

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Application Information
AC Link Serial Interface Protocol
AC Link Output Frame: SDATA_OUT (output from
controller, input to LM4549)
The audio output frame (output from AC ’97 Controller) con-
tains control and PCM data targeted for the LM4549 control
registers and stereo DAC. The Tag slot, slot 0, contains 16
bits that tell the AC Link interface circuitry on the LM4549 the
validity of the following data slots.
A new audio output frame is signaled with a low to high tran-
sition of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97
Controller drives SDATA_OUT with the first bit of slot 0. The
LM4549 samples SDATA_OUT on the falling edge of BIT-
_CLK. The AC ’97 Controller will continue outputting the
SDATA_OUT stream on each successive rising edge of BIT-
_CLK.
SDATA_OUT Slot 0: Tag Phase
The first bit of slot 0 is designated the Valid Frame bit. If
this bit is 1, it indicates that the current data frame contains
at least one slot of valid data and the LM4549 will further
sample the next four bits to determine which frames do in
fact have valid data. Valid slots are signified by a 1 in their re-
spective slot bit position.
FIGURE 3. AC 97 Bidirectional Audio Frame
FIGURE 4. AC Link Audio Output Frame
12
Bit
15
14
13
12
FIGURE 5. Start of Audio Output Frame
Left Playback
register data
Description
Valid Frame
PCM Data
address
register
Control
Control
1 = Control Data is valid.
1 = This frame has valid
1 = Control Address is
1 = Left PCM Data is
Comment
DS101035-4
valid.
valid.
data.
DS101035-6
DS101035-5

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