LM4560 National Semiconductor, LM4560 Datasheet
LM4560
Related parts for LM4560
LM4560 Summary of contents
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... The LM4560 supports multiple Rev 2.0 AC97 codecs, which are useful for notebook docking systems. With a low power, 3.3V process and a space conscious 100 TQFP package, the LM4560 is also well suited for Notebook systems. In summary, the LM4560 provides a balanced combination of features and performance to the end-user. By combining ...
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Features (Continued) n DirectX timer for video/audio synchronization n Forward pin-compatible with future PCI audio accelerators n 100-pin TQFP package n 3.3V operation Software Support n Complete DirectX driver suite (DirectSound3D, DirectSound, DirectMusic, and DirectInput) for Windows 95 and Windows ...
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... Timing 5.1.2.1 Slave read/write timing 6.0 Device Configuration 6.1 Overview 6.2 Configuration and GPIO Registers 7.0 Device Specifications 7.1 Absolute Maximum Ratings 7.2 Capacitance 7.3 Electrical Characteristics 7.4.1 Timing Table 7.4.2 PCI Signals Physical Dimensions List of Figures Figure 1. 100-Pin TQFP Package Figure 2. LM4560 Block diagram Figure 3. Wave Engine Block Diagram 3 www.national.com ...
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Pin Description 1.1 PACKAGE DIAGRAM www.national.com Top View FIGURE 1. 100-Pin TQFP Package 4 DS100910-2 ...
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Pin Description (Continued) 1.2 PIN DESCRIPTION Symbol Pin(s) Type Description V 20, 39, IN 3.3V Power Supply DD 52, 53, 69, 83, 100 V 11, 30, IN Ground SS 48, 60, 75, 90 PCI BUS INTERFACE SIGNALS (51) AD[31:0] ...
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... The enhanced mode works will all normal analog input joy- sticks. The CPU can read internal counters rather than mea- suring the time constants of each of the X, Y inputs with soft- ware timing loops. 2.1.1.3.6 The LM4560 supports the standard MPU 401 uart mode midi interface. 6 resistors are ...
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Register Description 3.1 PCI CONFIGURATION REGISTER MAP Offset +3h 00h 04h 08h 0Ch BIST 10h 14h 18–28h 2Ch 30h 34h 38h 3Ch MAX_LAT 40h 44h PM_Timer 48h DCh E0h Power Value Data 3.1.1 PCI Configuration Register Description 3.1.1.1 Device ...
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... DMA trapping is enable, the chip will handle DMA sta- tus read (I/O read port 8) depending on the DMA status mode bit. DMA status handle mode A: LM4560 will decode I/O read port 8 if StatusRDY is active, otherwise, it will ignore the cycle. DMA status handle mode B: 8 ...
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Register Description (Continued) When StatusRDY is not active, the chip will retry DMA status reads not the current active bus master. Whenever chip retry the DMA status read from other bus master, it will also generate ...
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Register Description 0: (Default) Normal (PME is controlled by bit[8] PME_En) 1: PME can be asserted independent of bit[8] (PME_En). Writing 0 to this bit has no effect. Writing 1 to this bit will clear this bit, and also ...
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Register Description (Continued) IO Offset +3h B0h MISCINT B4h START_B B8h STOP_B BCh CSPF_B C0h SBDMAL C4h SCE2R C8H STIMER CCh LFO_CTRL_B D0h ST_TARGET D4h RSVD D8h AINT_B DCh AINTEN_B E0h CSO E4h CPTR + LBA E8h ESO ECh ...
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Register Description 3.1.1.15.6 Legacy DMA Snooping: If CFG_REG45h[1] is ‘1’, Audio Processor will trap either of Legacy DMA channel snooping legacy DMA regis- ter 00h–0Fh write cycle and response to read cycle. Physically, these 16 ...
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Register Description (Continued) 3.4.1.2 DMAR1 (Legacy DMA Playback Buffer Base Register Port2) Address: DDMASlaveBase + 1h or AudioBase + 1h or 0000h / 0002h Size: 8 bits Type: Read/Write Default: 00h Write: Legacy DMA Playback Buffer Base Address 15–8 ...
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... Write: channel mode register for implemented legacy 8237-A DMA channel. Writing to this register will affect the legacy DMA operation of the LM4560, implementation of this register maintains the register compatibility with legacy 8237-A DMA channel mode register for system with or without DDMA Master. For system which has DDMA Master the DMA Master’ ...
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Register Description (Continued) Bit7..0 X Legacy FmMusic Bank 0 Register Index Read Bit 7 1 FmMusic Timer Interrupt Flag (Equal to Bit 6 + Bit 5) Bit 6 1 FmMusic Timer 1 Overflowed Flag Bit 5 1 FmMusic Timer2 ...
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Register Description Bit 7..0 X Legacy SB16 / SBPRO Mixer Register (indexed by SBR4) Data Port 3.4.2.7 SBR6 (Legacy Sound Blaster ESP Reset Port) Address: AudioBase + 16h or AudioBase + 17h or SBBase + 6h or SBBase + ...
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Register Description (Continued) Bit 7 0 Ack. Byte is available or External MIDI Input Data is Available in MDI-IN FIFO Acknowledfe Byte or External MIDI Input Data; Bit 6 0 Ready for MIDI Data Output or New ...
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Register Description When MPU-401 MIDI engine is at internal loopback opera- tion state (MPUR3.7 is set 1), MPUR1.7 is masked from MIDI-IN FIFO state automatically. This means if MIDI-IN FIFO is not empty, MPUR1.7 is still reading as 1. ...
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Register Description (Continued) Default: 00000000h Write Bit 7..0 X index of the AC-97 mixer register to be written; Bit for Primary CODEC; Bit for Secondary CODEC. Bit 14..7 X reserved Bit 15 0 ...
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Register Description 1: Enable (Default) Bit 17 (SURROUT_EN) SURROUT L/R Slot Enable 0: Disable 1: Enable Bit 18 (CENTEROUT_EN) CENTEROUT Slot Enable 0: Disable 1: Enable Bit 19 (LFEOUT_EN) LFEOUT Slot Enable 0: Disable 1: Enable Bit 20 (LINE1OUT_EN) ...
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Register Description (Continued) 10: SB ESP DMA Test Busy 11: SB ESP Command Buffer Full Bit ESP Engine at Digital Audio Off State 1: SB ESP Engine at Digital Audio On State Bit ...
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Register Description Type: Read/Write Default: 2h 3.4.7 OPL3 Channel Status Register These 4-byte registers can only be accessed on Audio Base (I/O or MEM). 3.4.7.1 AOPLSR0 (OPL3 Emulation Channel Key On/Off Trace Register) Address: AudioBase + 60h Size: 32 ...
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Register Description (Continued) This bit will be set from ‘0’ to ‘1’ only when a ‘1’ is written to the corresponding bit in register START_A. Writing to this I/O port means issuing a start command to ad- dress engine ...
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Register Description A ‘1’ written to bit n will reset this bit. 3.4.9.8 EINT (Envelope Engine Interrupt Eegister) (for Bank A only) Address: AudioBase + 9Ch Size: 32 bits Type: Read/Write Default: 00000000h Any bits toggled from ‘0’ to ...
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Register Description (Continued) Note: Controlled by PCMIN_SEL in Reg48h, either of Primary CODEC PC- MIN slot or Secondary CODEC PCMIN slot will come into 3-level PC- MIN_A buffer. And if PCMIN_B Mixing bit is enabled, the other slot will ...
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Register Description Bit 2 (SB_IRQ) is sound blaster IRQ bit. Active high. Bit[2] = sbirq (signal from Legacy Audio block) Bit 3 (MPU401_IRQ) is MPU401 IRQ bit. Active high. Bit[3] = mpu401irq (signal from Legacy Audio block) Bit 4 ...
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Register Description (Continued) This register will show a flag which indicates the Bank B’s current sample range between ESO/2 to ESO range before ESO/2 (ESO is offset from loop begin to loop end). ...
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Register Description 3.4.9.21 ST_TARGET (Sample Timer Target) Address: AudioBase + D0h Size: 32 bits Type: Read/Write Default: 00000000h Bit 31–0 (ST_TARGET) is used to store a pre-set value. Once STIMER counter reaches that value, an IRQ called ST_IRQ will ...
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Register Description (Continued) CVOL — Chorus Send Linear Volume (7 bit) Bit[31:28] (SIN) Sine wave value. Bit[27] (SIN_S) sign bit of sine wave. 0: positive 1: negative Bit[26] (SIN_D) SIN counter direction bit down Bit[25:24] (LFO_R) ...
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Register Description when Bit[31:30 (REC or REC_PB) 00: left, 01: right 10: (left+right+1)/2 11: reserved. Bit[23] SRC Enable 0 disable 1 enable Bit[22] FM and AM Enable 0 disable 1 enable Bit[21] PAN Enable 0 disable 1 ...
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... Base + 818h + 20h*CIR (direct access mode, CIR: channel index) (CIR Size: 32 bits Type: Read/Write Default: XXXXXXXXh Description: Envelope Buffer 2 EBUF2 is totally as the same as EBUF1 except that bits 31–30 are AMS_L (Amplitude Modulation Step Low part). FIGURE 2. LM4560 Block Diagram 31 < 32) DS100910-1 www.national.com ...
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Functional Description 4.1 WAVE ENGINE Feature: • 64 voice synthesis • Each voice channel typically consumes 0.25% PCI band- width • 8/16 bits, mono/stereo, unsigned/signed samples at arbi- trary sample rate • Unlimited length of wave samples • Internal ...
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Functional Description • Channels which don’t require PCI bus cycle, i.e. cache hit channels and I2StoMIX channel, have lower priority. Basically, all operation of one channel include address generation, data reading/writing, interpolation, per channel LFO, low fre- quency FM/AM, ...
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Functional Description 4.1.3 Envelope engine Low frequency AM, Envelope calculation and PAN are processed by Envelope Engine. Terms: Ec (12 bits) — Current envelope value in format of 6.6 AMS_H (2 bits) — Higher 2 bits of AMS AMS_L ...
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Functional Description If sample is stereo, there are two data inputs — D_L and D_R, if sample is mono, only one data input — D. All this data should be converted to 16-bit signed format. Conversion from unsigned data ...
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Functional Description www.national.com (Continued) SIN[3:0] SIN_S ...
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Functional Description SIN[3:0] One cycle of SIN counter 4.1.7 Recording A down sampling SRC is used for recording. 4.1.8 PCI Buffer/Sample Cache PCI Buffer (or called Sample Cache 128x32 bit SRAM which is designed to reduce consumption ...
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Functional Description Table CODEC Buffer Partitioning 4.1.10 Legacy Channel Playback/Recording This function block is intended to emulate legacy DMA using PCI bus master engine. All parameters used by this Legacy Channel are stored in register. LBL CA[1:0] 00 SB_Data_type[2:1]=00 ...
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Functional Description will generate an interrupt and wait for next command. • Continuous DMA Mode SB ESP is programmed to make continuous transfer to/ from CODEC. After each transfer of a specified block size, the SB ESP will generate ...
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Functional Description 1 Reserved 4.2.1.5.2 Command 10h Function: 8-bit direct mode playback 4.2.1.5.3 Command 14h Function: 8-bit normal DMA playback Length = number of bytes to be transferred - 1 SB ESP will generate an interrupt after the specified ...
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Functional Description 4.2.1.7.2 Command 41h Function: Set Playback Sample Rate by Frequency Sampling Frequency = 4 kHz to 48 kHz, either mono or stereo 4.2.1.7.3 Command 42h Function: Set Recording Sample Rate by Frequency Sampling Frequency = 4 kHz ...
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Functional Description 4.2.1.10.2 COMMAND 90H Function: 8-bit continuous special DMA playback SB ESP will generate an interrupt after each block length of data has been transferred. 4.2.1.10.3 Command 91h Function: 8-bit non-continuous special DMA playback SB ESP will generate ...
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Functional Description Bit 3..0 X reserved Length = number of words to be transferred -1 For non-continuous DMA, SB ESP will generate an interrupt and terminate the DMA transfer after the specified length of data has been transferred. For ...
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Functional Description 4.2.1.13 8/16-Bit Audio Dma Operation Control Command Dxh 4.2.1.13.1 Command D0h Function: Pause Non-Bx Type Command DMA Transfer The DMA request is stopped after this command. Internal FIFO will continue running until the FIFO is empty (playback) ...
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Functional Description E2h command is used to compute the subroutine’s starting address for digital sound playback or recording according to the dedi- cated algorithm. The resultant byte should be sent back to system memory via legacy DMA operation method ...
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Functional Description All of the legacy sound blaster mixer register except MX80, MX81 and MX82 are implemented virtually using the opl3 emulation RAM (512 bytes). Please refer to section 2.3 to get detailed description of the virtual implementation method. ...
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Functional Description Bit 5 output filter enable Bit 4..2 reserved Bit 1 stereo switch Bit 0 reserved Output filter enable is dummy read/write bit for SB PRO com- patibility. Output filter enable output low-pass filter on, 1 ...
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Functional Description Read/Write Bit 7..3 32 level external line left volume Bit 2..0 reserved 0 mute (maximum volume) MX39 External Line Right Volume Default 00h Read/Write Bit 7..3 32 level external line right volume Bit 2..0 ...
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Functional Description Read/Write Bit reserved 7..1 Bit 0 0 AGC disable 1 AGC enable MX44 Treble Left Control Default 80h Read/Write Bit 7..4 16 level treble left control Bit 3..0 reserved MX45 Treble Right Control Default 80h Read/Write Bit ...
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Functional Description Default: FFh Bit 7..0 Low Byte of SB DMA Current Block Length Re- mained - 1 4.2.1.22.2.4 SBDMAC SB DMA Current Block Length High Byte SB ESP Address: 1h Size: 8 bits Type: Write Only For SB ...
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Functional Description Present Next State Change Way State State D0 D1 HIFW HIFW D1 5.1.2 Timing The timing descriptions of host interface signals. All signal’s transition edges are respected to the rising edge of PCICLK. The ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Voltage ( 7.2 CAPACITANCE ± 0˚C to 70˚ 3.3V 5 Symbol Parameter C Input Pin Capacitance IN C Clock Input Capacitance ...
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Timing Table (Continued) ± 0˚C to 70˚ 3.3V 5 Symbol PCI Reset Trst_low RST # low time after power stable Trst_clk RST # low time after PCICLK stable AC’97 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 100-Pin Thin Plastic Quad Flatpak Order Number LM4560VJD NS Package Number VJD100A 2 ...