LM4842 National Semiconductor, LM4842 Datasheet - Page 20

• Manufacturer Part Number: LM4842
• Description: Stereo 2W Amplifiers with DC Volume Control Transient Free Outputs/ and Cap-less Headphone Drive
• Manufacturer: National Semiconductor

www.national.com
Application Information
As an example when using a speaker with a low frequency
limit of 150Hz, the input coupling capacitor using Equation
(7), is 0.053µF. The 0.33µF input coupling capacitor shown
in Figure 1 allows the LM4842 to drive high efficiency, full
range speaker whose response extends below 30Hz.
TURN ON Characteristics
The LM4842 contains advanced circuitry that minimizes
turn-on and shutdown transients or “clicks and pops”. For
this discussion, turn-on refers to either applying the power
supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the
LM4842’s internal amplifiers are configured as unity gain
buffers. An internal current source changes the voltage of
the BYPASS pin in a controlled, linear manner. Ideally, the
input and outputs track the voltage applied to the BYPASS
pin. The gain of the internal amplifiers remains unity until the
voltage on the BYPASS pin reaches 1/2 V
voltage on the BYPASS pin is stable, the LM4842 is ready to
be fully turned on. To turn the device on, the input signal
must exceed 22mV
threshold detect circuit that enables all appropriate output
amplifiers after the 22mVrms limit is reached. Until this
threshold is reached, some of the amplifiers remain in a
tri-state mode. This insures that there is no current flowing
through to the speakers or headphones during power up.
Without current flow, the speakers or headphones remain
silent. During headphone mode, A+, B-, and B+ are in tri-
state mode during power up. During speaker mode, A+ and
B+ are in tri-state mode during power up.
Although the BYPASS pin current cannot be modified,
changing the size of C
time. As the size of C
increases. There is a linear relationship between the size of
C
times for various values of C
DOCKING STATION INTERFACE
Applications such as notebook computers can take advan-
tage of a docking station to connect to external devices such
as monitors or audio/visual equipment that sends or receives
line level signals. The LM4842 has two outputs, Dock A and
Dock B, which connect to outputs of the internal input am-
plifiers that drive the volume control inputs. These input
amplifiers can drive loads of
ers) with a rail-to-rail signal. Since the output signal present
on the Dock A and Dock B pins are biased to V
capacitors should be connected in series with the load when
BYPASS
and the turn-on time. Here are some typical turn-on
C
BYPASS
rms
0.01µF
0.22µF
0.47µF
0.1µF
1.0µF
BYPASS
. This is accomplished through a
BYPASS
>
BYPASS
1kΩ (such as powered speak-
increases, the turn-on time
alters the device’s turn-on
:
T
ON
200ms
20ms
44ms
94ms
2ms
DD
(Continued)
. As soon as the
DD
/2, coupling
(7)
20
using these outputs. Typical values for the output coupling
capacitors are 0.33µF to 1.0µF. If polarized coupling capaci-
tors are used, connect their ’+’ terminals to the respective
output pin.
Since the Dock outputs precede the internal volume control,
the signal amplitude will be equal to the input signal’s mag-
nitude and cannot be adjusted. However, the input amplifi-
er’s closed-loop gain can be adjusted using external resis-
tors. These 20k resistors (R
2 and they set each input amplifier’s gain to -1. Use Equation
7 to determine the input and feedback resistor values for a
desired gain.
Adjusting the input amplifier’s gain sets the minimum gain for
that channel. Although the single ended output of the Bridge
Output Amplifiers can be used to drive line level outputs, it is
recommended that the A & B Dock Outputs simpler signal
path be used for better performance.
MUX CONTROL AND MODE PINS
The LM4842 has two pairs of stereo inputs. The MUX CON-
TROL pin determines which of these stereo pairs of inputs
are active. Applying 0V to the MUX CONTROL pin (with the
Mode pin tied low) selects inputs A0 and B0. Applying V
the MUX CONTROL (with the Mode pin tied low) pin selects
inputs A1 and B1 (See Truth Table for Logic Inputs).
When the Mode pin is pulled high the MUX Control is dis-
abled and the Headphone Sense Pin controls the A and B
input pairs as follows:
lects inputs A1 and B1.
selects inputs A0 and B0.
When the MODE pin is high the HP SENSE controls the
MUX inputs. This configuration can be very useful, for ex-
ample, when the headphone acoustic output needs to be
much lower than the BTL Speaker Output. Two different
gains can be hardwired into the two pairs of MUX input
circuits. This allows the user to have the HP SENSE auto-
matically change the output level for either of the MUX input
pairs by switching between the two pairs of MUX inputs, if
the same input signal is connected to both MUX inputs.
When the MODE pin is low the MUX pin switches the MUX
input pairs directly.
BEEP DETECT FUNCTION
Computers and notebooks produce a system ’beep’ signal
that drives a small speaker. The speaker’s auditory output
signifies that the system requires user attention or input. To
accommodate this system alert signal, the LM4842’s beep
input pin is a mono input that accepts the beep signal.
Internal level detection circuitry at this input monitors the
beep signal’s magnitude. When a signal level greater than
V
amplifiers are enabled. The beep signal is amplified and
applied to the load connected to the output amplifiers. A valid
beep signal will be applied to the load even when MUTE is
active. Use the input resistors connected between the BEEP
IN pin and the stereo input pins to accommodate different
beep signal amplitudes. These resistors are shown as
200kΩ devices in Figure 1. Use higher value resistors to
reduce the gain applied to the beep signal. The resistors
must be used to pass the beep signal to the stereo inputs.
DD
Headphone Sense enabled (Headphone plugged in) se-
Headphone Sense disabled (Headphone not plugged in)
/2 is detected on the BEEP IN pin, the bridge output
- A
v
= R
FA
and R
F
/ R
IN
FB
) are shown in Figure
DD
(8)
to