MC54HC162 Motorola, MC54HC162 Datasheet - Page 5

• Manufacturer Part Number: MC54HC162
• Description: (MC54HC160 / MC54HC162) Presettable Counters
• Manufacturer: Motorola

High–Speed CMOS Logic Data
DL129 — Rev 6
counters that feature parallel Load, synchronous or asynch-
ronous Reset, a Carry Output for cascading, and count–
enable controls.
nous Reset, and synchronous Reset, respectively.
INPUTS
Clock (Pin 2)
vances with the rising edge of the Clock input. In addition,
control functions, such as resetting (HC162) and loading
occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
Data on these pins may be synchronously loaded into the in-
ternal flip–flops and appear at the counter outputs. P0 (pin 3)
is the least–significant bit and P3 (pin 6) is the most–signifi-
cant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
is the least–significant bit and Q3 (pin 11) is the most–signifi-
cant bit.
Ripple Carry Out (Pin 15)
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Rip-
ple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
The HC160/162 are programmable 4–bit synchronous
The HC160 and HC162 are BCD counters with asynchro-
The internal flip–flops toggle and the output count ad-
These are the data inputs for programmable counting.
These are the counter outputs (BCD or binary). Q0 (pin 14)
When the counter is in its maximum state (1001 for the
Ripple Carry Out = Enable T
FUNCTION DESCRIPTION
for BCD counters HC160 and
HC162

Q0

Q1
15
14
13
12
0

HC160 and HC162 BCD Counters
Q2
OUTPUT STATE DIAGRAMS

Q3
11
1
10
2
5
CONTROL FUNCTIONS
Resetting
flops and sets the outputs (Q0 through Q3) to a low level.
The HC160 resets asynchronously and the HC162 resets
with the rising edge of the Clock input (synchronous reset).
Loading
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
may be programmed to any state. If they are loaded with a
state disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output
State Diagram).
Count Enable/Disable
able P (pin 7) and Enable T (pin 10). The devices count when
these two pins and the Load pin are high. The logic equation
is:
puts according to Table 1. In general, Enable P is a count–
enable control; Enable T is both a count–enable and a
Ripple–Carry Output control.
* Q0 through Q3 are maximum for the HC160 and HC162 when
Q3 Q2 Q1 Q0 = 1001.
Load
A low level on the Reset pin (pin 1) resets the internal flip–
With the rising edge of the Clock, a low level on Load (pin
Although the HC160 and HC162 are BCD counters, they
These devices have two count–enable control pins: En-
The count is either enabled or disabled by the control in-
Control Inputs
H
X
X
L
3
9
Count Enable = Enable P
Enable P
H
H
X
L
Table 1. Count Enable/Disable
4
5
6
7
8
MC54/74HC160 MC54/74HC162
Enable T
H
H
H
L
No Count
No Count
No Count
Result at Outputs
Q0 – Q3
Count

Enable T
High when Q0 – Q3
High when Q0 – Q3
are maximum*
are maximum*
High when Q0 – Q3
are maximum*
Ripple Carry Out

Load
MOTOROLA
L