MC56F8037 Motorola Semiconductor, MC56F8037 Datasheet - Page 3
MC56F8037
Manufacturer Part Number
MC56F8037
Description
Digital Signal Controller
Manufacturer
Motorola Semiconductor
Datasheet
1.MC56F8037.pdf
(12 pages)
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Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard
architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Dual Harvard architecture permits as many as three simultaneous accesses to program and data
memory
Flash security and protection that prevent unauthorized users from gaining access to the internal
Flash
On-chip memory:
— 64KB of Program Flash
— 8KB of Unified Data/Program RAM
EEPROM emulation capability using Flash
One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and Edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
Digital Signal Controller Core
Memory
Peripheral Circuits for 56F8037
56F8037 Digital Signal Controller Product Brief, Rev. 0
Preliminary—Subject to Change Without Notice
Digital Signal Controller Core
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