MC56F8367 Freescale Semiconductor, MC56F8367 Datasheet - Page 127

• Manufacturer Part Number: MC56F8367
• Description: (MC56F8167 / MC56F8367) 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor

6.5.10.2
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.5.11
The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a
power-saving feaure. The clocks can be individually controller for each peripheral on the chip.
6.5.11.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.11.2
Each bit controls clocks to the indicated peripheral.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused sub-functions. Refer to
Peripheral User Manual for further details.
Freescale Semiconductor
Preliminary
•
•
Base + $E
Base + $D
RESET
RESET
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Write
Write
Read
Read
Peripheral Clock Enable Register 2 (SIM_PCE2)
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
Reserved—Bits 15–1
CAN2 Enable—Bit 0
Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)
15
15
1
0
0
14
14
1
0
0
13
13
1
0
0
12
12
1
0
0
56F8367 Technical Data, Rev. 7.0
11
11
1
0
0
Part 3 On-Chip Clock Synthesis
10
10
1
0
0
9
1
9
0
0
8
8
1
0
0
ISAL[21:6]
7
7
1
0
0
6
6
1
0
0
5
5
1
0
0
4
4
1
0
0
(OCCS), and the 56F8300
3
3
1
0
0
Clock Generation Overview
2
2
1
0
0
1
1
1
0
0
CAN
0
0
1
2
1
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