MC74F112 Motorola, MC74F112 Datasheet

MC74F112

Manufacturer Part Number

MC74F112

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacturer

Motorola

Datasheet

1.MC74F112.pdf (3 pages)

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DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

rect Set and Clear inputs. Synchronous state changes are initiated by the fal-

ling edge of the clock. Triggering occurs at a voltage level of the clock and is

not directly related to the transition time. The J and K inputs can change when

the clock is in either state without affecting the flip-flop, provided that they are

in the desired state during the recommended setup and hold times relative to

the falling edge of the clock. A LOW signal on S D or C D prevents clocking and

forces Q or Q HIGH, respectively. Simultaneous LOW signals on S D and C D

force both Q and Q HIGH.

The MC74F112 contains two independent, high-speed JK flip-flops with Di-

FUNCTION TABLE (Each Half)

Asynchronous Inputs:

H = HIGH Voltage Level

L = LOW Voltage Level

t n = Bit time before clock pulse

t n + 1 = Bit time after clock pulse

LOW Input to S D sets Q to HIGH level

LOW Input to C D sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C D and S D makes both Q and Q HIGH

V CC C D1 C D2 CP 2

CP 1

Inputs

@ t n

CONNECTION DIAGRAM

K 1

C D

S D

J 1

S D1

K 2

Q 1

J 2

S D

C D

FAST AND LS TTL DATA

S D2

Q 2

@ t n + 1

Output

Q n

GND

Q 2

4-45

EDGE-TRIGGERED FLIP-FLOP

ORDERING INFORMATION

FAST

MC74FXXXJ

MC74FXXXN

MC74FXXXD

DUAL JK NEGATIVE

S D

MC74F112

LOGIC SYMBOL

V CC = PIN 16

GND = PIN 8

SCHOTTKY TTL

Ceramic

Plastic

SOIC

CASE 751B-03

CASE 620-09

CASE 648-08

CERAMIC

N SUFFIX

D SUFFIX

J SUFFIX

PLASTIC

SOIC

C D

S D

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MC74F112 Summary of contents

Page 1

... DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The MC74F112 contains two independent, high-speed JK flip-flops with Di- rect Set and Clear inputs. Synchronous state changes are initiated by the fal- ling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when ...

Page 2

... I CC Power Supply Current NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. MC74F112 LOGIC DIAGRAM (one half shown) Min 74 4.5 74 ...

Page 3

... Hold Time, HIGH or LOW Pulse Width, HIGH t w (L) or LOW Pulse Width, LOW Recovery Time t rec MC74F112 74F + +5 Min Max 110 2.0 6.5 2.0 6.5 2 ...

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