MC74F195 Motorola, MC74F195 Datasheet

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MC74F195

Manufacturer Part Number
MC74F195
Description
4-BIT PARALLEL ACCESS SHIFT REGISTER
Manufacturer
Motorola
Datasheet
4-BIT PARALLEL
ACCESS SHIFT REGISTER
Register are indicated in the Logic Diagram and Function Table. The device
is useful in a wide variety of shifting, counting, and storage applications. It per-
forms serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at
very high speeds.
allel load, which are controlled by the state of the Parallel Enable (PE) input.
Serial data enters the first flip-flop (Q 0 ) via the J and K inputs when the PE
input is HIGH, and is shifted 1 bit in the direction Q 0 -Q 1 -Q 2 -Q 3 following each
LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the
JK type input is made for special applications, and by tying the two pins togeth-
er the simple D-type input is made for general applications. The device ap-
pears as four common clocked D flip-flops when the PE input is LOW. After
the LOW-to-HIGH clock transition, data on the parallel inputs (D 0 -D 3 ) is trans-
ferred to the respective Q 0 -Q 3 outputs. Shift left operation (Q 3 -Q 2 ) can be
achieved by tying the Q n outputs to the D n-1 inputs and holding the PE input
LOW.
LOW-to-HIGH clock transition. The MC74F195 utilizes edge-triggering;
therefore, there is no restriction on the activity of the J, K, D n , and PE inputs
for logic operation, other than the setup and hold time requirements.
LOW, independent of any other input condition.
The functional characteristics of the MC74F195 4-Bit Parallel Access Shift
The MC74F195 operates in two primary modes, shift right (Q 0 -Q 1 ) and par-
All parallel and serial data transfers are synchronous, occurring after each
A LOW on the asynchronous Master Reset (MR) input sets all Q outputs
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
V CC
MR
16
1
CONNECTION DIAGRAM DIP
Q 0
15
2
J
Q 1
14
3
K
Q 2
D 0
13
4
Q 3
D 1
12
5
Q 3
D 2
11
6
FAST AND LS TTL DATA
CP
10
D 3
7
GND
PE
9
8
4-104
16
16
ACCESS SHIFT REGISTER
10
16
ORDERING INFORMATION
3
2
1
1
MC74FXXXJ
MC74FXXXN
MC74FXXXD
FAST
MC74F195
4-BIT PARALLEL
1
LOGIC SYMBOL
CP
J
K
MR Q 0 Q 1 Q 2 Q 3
9
PE D 0 D 1 D 2 D 3
1 15 14 13 12
V CC = PIN 16
GND = PIN 8
SCHOTTKY TTL
4
5
Ceramic
Plastic
SOIC
6
CASE 751B-03
CASE 620-09
CASE 648-08
7
CERAMIC
N SUFFIX
D SUFFIX
J SUFFIX
PLASTIC
Q 3
SOIC
11

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MC74F195 Summary of contents

Page 1

... The MC74F195 operates in two primary modes, shift right ( and par- allel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop ( via the J and K inputs when the PE input is HIGH, and is shifted 1 bit in the direction following each LOW-to-HIGH clock transition ...

Page 2

... Parallel Load H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. = LOW-to-HIGH clock transition MC74F195 Parameter LOGIC DIAGRAM ...

Page 3

... Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS Symbol Parameter f max t PLH Propagation Delay t PHL CP to Q/Q t PHL Propagation Delay PLH Propagation Delay MC74F195 Limits Min Typ Max Unit 2.0 V 0.8 V –1 ...

Page 4

... Setup Time, HIGH or LOW ( (H) Hold Time, HIGH or LOW ( (H) CP Pulse Width, HIGH t w (L) MR Pulse Width, LOW t rec Recovery Time MC74F195 74F 5 5 Min Max Min 4.0 4 ...

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