MC74LCX573 ON Semiconductor, MC74LCX573 Datasheet

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MC74LCX573

Manufacturer Part Number
MC74LCX573
Description
Low-Voltage CMOS Octal Transparent Latch
Manufacturer
ON Semiconductor
Datasheet

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MC74LCX573
Low−Voltage CMOS
Octal Transparent Latch
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A V
MC74LCX573 inputs to be safely driven from 5.0 V devices.
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn
inputs enters the latches. In this condition, the latches are transparent,
i.e., a latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW transition
of LE. The 3−state standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The LCX573 flow through design facilitates easy PC
board layout.
Features
*For additional information on our Pb−Free strategy and soldering details, please
May, 2005 − Rev. 7
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74LCX573 is a high performance, non−inverting octal
The MC74LCX573 contains 8 D−type latches with 3−state standard
Substantially Reduces System Power Requirements
Designed for 2.3 to 3.6 V V
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
I
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Latchup Performance Exceeds 500 mA
ESD Performance:
Pb−Free Packages are Available*
Semiconductor Components Industries, LLC, 2005
OFF
Specification Guarantees High Impedance When V
Human Body Model >2000 V
Machine Model >200 V
CC
Operation
I
specification of 5.5 V allows
www.DataSheet4U.com
CC
1
= 0 V
20
20
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
20
1
1
1
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
http://onsemi.com
CASE 948E
SOEIAJ−20
TSSOP−20
DT SUFFIX
CASE 967
DW SUFFIX
M SUFFIX
CASE 751D
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
SOIC−20
Publication Order Number:
20
1
20
20
1
1
DIAGRAMS
AWLYYWWG
MARKING
MC74LCX573/D
AWLYWWG
74LCX573
ALYWG
LCX573
LCX
573
G

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MC74LCX573 Summary of contents

Page 1

... TTL compatible outputs offer improved switching noise performance MC74LCX573 inputs to be safely driven from 5.0 V devices. The MC74LCX573 contains 8 D−type latches with 3−state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i ...

Page 2

... Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition Change, State Prior to the Latch Enable High−to−Low Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For I Reasons DO NOT FLOAT Inputs CC MC74LCX573 ...

Page 3

... Device MC74LCX573DW MC74LCX573DWG MC74LCX573DWR2 MC74LCX573DWR2G MC74LCX573DT MC74LCX573DTG MC74LCX573DTR2 MC74LCX573DTR2G MC74LCX573M MC74LCX573MG MC74LCX573MEL †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MC74LCX573 Value −0.5 to +7.0 − ...

Page 4

... OSLH 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t guaranteed by design. MC74LCX573 Condition 2 2 ...

Page 5

... PLH PHL On 1.5 V WAVEFORM 3 − PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES 2.5 ns, 10 MHz MC74LCX573 Condition ...

Page 6

... MC74LCX573 PULSE GENERATOR R T TEST PLH PHL PZL PLZ Open Collector/Drain t and t PLH PHL PZH PHZ = 3.3 0 equivalent (includes jig and probe capacitance 2.5 0 equivalent (includes jig and probe capacitance 500 W or equivalent ...

Page 7

... L PIN 1 IDENT 1 0.15 (0.006 −V− 0.100 (0.004) −T− SEATING PLANE MC74LCX573 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE SEATING PLANE C T TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE ...

Page 8

... BSC H 7.40 8.20 0.291 0.323 E L 0.50 0.85 0.020 0.033 L 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 1 Z −−− 0.81 −−− 0.032 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC74LCX573/D ...

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