LMX2471 National Semiconductor, LMX2471 Datasheet - Page 19

• Manufacturer Part Number: LMX2471
• Description: 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
• Manufacturer: National Semiconductor

Functional Description
1.4 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of 10 nS. To enter the locked state
(Lock = HIGH) the phase error must be less than the 10nS
RC delay for 5 consecutive reference cycles. Once in lock
(Lock = HIGH), the RC delay is changed to approximately
20nS. To exit the locked state (Lock = LOW), the phase error
must become greater than the 20nS RC delay. When the
PLL is in the power down mode, Lock is forced LOW. For the
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RF PLL, the digital lock detect circuitry does not function
reliably for comparison frequencies above 20 MHz.
The IF PLL digital lock detect circuitry works in a very similar
way as the RF PLL digitial lock circuitry, except that it uses a
delay of less than 15 nS for 5 reference cycles to determine
a locked condition and a delay of greater than 30 nS to
determine the IF PLL is unlocked. Note that if the MUX[3:0]
word is set such as to view lock detect for both PLLs, an
unlocked (LOW) condition is shown whenever either one of
the PLLs is determined to be out of lock. A flow chart of the
IF digital lock detect circuitry is shown below.
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