HT47C20 Holtek Semiconductor Inc, HT47C20 Datasheet - Page 15

• Manufacturer Part Number: HT47C20
• Description: 8-Bit Microcontroller
• Manufacturer: Holtek Semiconductor Inc

External interrupt is triggered by a high to low
transition of INT and the related interrupt re-
quest flag (EIF; bit 4 of INTC0) will be set.
When the interrupt is enabled, and the stack is
not full and the external interrupt is active, a
subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will
be cleared to disable other interrupts.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 4 of INTC1),
caused by a timer A or timer B overflow. When
the interrupt is enabled, and the stack is not
full and the TF bit is set, a subroutine call to lo-
cation 10H will occur. The related interrupt re-
quest flag (TF) will be reset and the EMI bit
cleared to disable further interrupts.
The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 5
of INTC0), caused by a regular time base sig-
nal. When the interrupt is enabled, and the
stack is not full and the TBF bit is set, a subrou-
tine call to location 08H will occur. The related
interrupt request flag (TBF) will be reset and
the EMI bit cleared to disable further inter-
rupts.
The real time clock interrupt is initialized by
setting the real time clock interrupt request
flag (RTF; bit 6 of INTC0), caused by a regular
real time clock signal. When the interrupt is en-
abled, and the stack is not full and the RTF bit
is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (RTF)
will be reset and the EMI bit cleared to disable
further interrupts.
During the execution of an interrupt subrou-
tine, other interrupt acknowledgments are held
until the RETI instruction is executed or the
EMI bit and the related interrupt control bit
are set to 1 (if the stack is not full). To return
from the interrupt subroutine, RET or RETI in-
struction may be invoked. RETI will set the
EMI bit to enable an interrupt service, but RET
does not.
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Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
The external interrupt request flag (EIF), real
time clock interrupt request flag (RTF), time base
interrupt request flag (TBF), enable external in-
terrupt bit (EEI), enable real time clock interrupt
bit (ERTI), enable time base interrupt bit (ETBI),
and enable master interrupt bit (EMI) constitute
an interrupt control register 0 (INTC0) which is
located at 0BH in the data memory. The
timer/event counter interrupt request flag (TF),
enable timer/event counter interrupt bit (ETI) on
the other hand, constitute an interrupt control
register 1 (INTC1) which is located at 1EH in the
data memory. EMI, EEI, ETI, ETBI, and ERTI
are used to control the enabling/disabling of in-
terrupts. These bits prevent the requested inter-
rupt being serviced. Once the interrupt request
flags (RTF, TBF, TF, EIF) are set, they remain in
the INTC1 or INTC0 respectively until the inter-
rupts are serviced or cleared by a software in-
struction.
It is recommended that a program does not use
the ²CALL subroutine² within the interrupt
subroutine. Because interrupts often occur in
an unpredictable manner or need to be serviced
immediately in some applications, if only one
stack is left, and enabling the interrupt is not
well controlled, once the ²CALL subroutine² op-
erates in the interrupt subroutine will damage
the original control sequence.
No. Interrupt Source Priority Vector
a
b
d
c
External interrupt
Time base interrupt
Real time clock
interrupt
Timer/event counter
interrupt
January 18, 2000
1
2
3
4
HT47C20
0CH
04H
08H
10H