HT48CA3 Holtek Semiconductor Inc, HT48CA3 Datasheet - Page 5

• Manufacturer Part Number: HT48CA3
• Description: 8-Bit Remote Type MCU
• Manufacturer: Holtek Semiconductor Inc

Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192 16 bits 3 banks, addressed by the program coun-
ter and table pointer.
Certain locations in the program memory are reserved
for special usage:
Note: *14~*0: Table location bits
Rev. 1.40
TABRDC [m]
TABRDL [m]
Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Location 008H
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the in-
terrupt is enabled and the stack is not full, the program
begins execution at location 008H.
Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Table location
Any location in the program memory can be used as
look-up tables. The instructions TABRDC [m] (page
specified by TBHP) and TABRDL [m] (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH(08H). The higher-order byte table pointer
TBHP(1FH) and lower-order byte table pointer TBLP
(07H) are read/write registers, which indicate the table
locations. Before accessing the table, the location has
to be placed in TBHP and TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (interrupt service routine) both employ the ta-
ble read instruction, the contents of TBLH in the main
routine are likely to be changed by the table read in-
struction used in the ISR. Errors are thus brought
about. Given this, using the table read instruction in
the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both main routine and the ISR, the in-
Instruction
1011111
*14~*8
TBHP
@7
@7
*7
@6
@6
*6
Table location
@5
@5
5
*5
Table Location
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
@7~@0: Table pointer bits
terrupt(s) is supposed to be disabled prior to the table
read instruction. It (They) will not be enabled until the
TBLH in the main routine has been backup. All table
related instructions require 2 cycles to complete the
operation.
@4
@4
*4
@3
@3
*3
Program memory
@2
@2
*2
@1
@1
*1
HT48CA3
July 16, 2003
@0
@0
*0