PDSP16116AB0GG Mitel Networks Corporation, PDSP16116AB0GG Datasheet
PDSP16116AB0GG
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PDSP16116AB0GG Summary of contents
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Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup- port Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply ...
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PDSP16116 SYSTEM FEATURES The PDSP16116 has a number of features tailored for sys- tem applications. (21)3(21) Trap In multiply operations using two’s complement fractional no- tation, the (21)3(21) operation forms an invalid result because 11 is not representable in the ...
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XR15:0 REG C 16316 O M MULT P ‘1’ MUX REG OVR CLK WTA AR15:13 WTB AI15:13 INTERNAL CONTROL SOBPF SIGNALS LOGIC EOPSS SFTR SFTA GWR4:0 WTOUT OER Fig. 2 PDSP16116 Block diagram CEX XI15:0 YR15:0 CEY REG REG C ...
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PDSP16116 Fig. 3a Pin connections for 144 I/O power pin grid array package (bottom view) Fig. 3b Pin connections for 144 I/O ceramic quad ...
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Signal PI14 PI15 WTOUT1 WTOUT0 SFTR0 SFTR1 SFTR2 OEI CONY ...
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PDSP16116 NORMAL MODE OPERATION When the MBFP mode select input is held low the ‘Normal’ mode of operation is selected. This mode supports all complex multiply operations that do not require block floating point arithmetic. Complex two’s complement fractional data ...
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Shifter Each of the two adder/subtractors are followed by shifters controlled via the WTB control input. These shifters can each apply two different shifts; however, the same shift is applied to both real and imaginary components. The four shift options ...
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PDSP16116 MBFP Mode select. When high, block floating point (BFP) mode is selected. This allows the device to maintain the dynamic range of the data using a series of word tags. This is especially useful in FFT applications. When low, ...
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OSEL1 :0 The outputs from the device are selected by the OSEL0 and OSEL1 instruction bits. These controls allow selection of the output combination during the current cycle (they are not registered). There are four possible output configurations that allow ...
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PDSP16116 The butterfly operation The butterfly operation is the arithmetic operation which is repeated many times to produce an FFT. The PDSP16116- based butterfly processor performs this operation in a low power high accuracy chip set. A A′ = A1BW ...
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CLK SOBFP EOPSS WTA, WTB A′, B′, BTOUT GWR START OF FIRST PASS In practice, data output may never approach the theoretical maximum. Hence, it may be worthwhile to try various universal exponents ...
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PDSP16116 OUTPUT P PORTS OUTPUT SFTA1:0 INPUT DATA X AND Y INPUT CONTROLS CEX AND CEY INPUT CONTROLS CONX AND CONY INPUT CONTROL WTB1:0 OER AND OEI t OPLZ OUTPUT P PORTS HIGH Z Test Waveform measurement level Delay from ...
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ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated 15V±10%, GND = 0V Static Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input high voltage ...
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PDSP16116 ABSOLUTE MAXIMUM RATINGS (NOTE 1) Supply voltage Input voltage Output voltage, V OUT Clamp diode current per pin, I (see note 2) K Static discharge voltage (HBM) Storage temperature Ambient temperature with power ...
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