PDSP16488A0 Mitel Networks Corporation, PDSP16488A0 Datasheet
PDSP16488A0
Related parts for PDSP16488A0
PDSP16488A0 Summary of contents
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Supersedes version in 1996 Media IC Handbook, HB4599-1.0 and the PDSP16488A MA data sheet, DS3742 The PDSP16488A is a fully integrated, application specific, image processing device. It performs a two dimensional convo- lution between the pixels within a video window ...
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Signal Type IP7:0 Input L7:0 I/O BYPASS Input HRES Input X15:0 Dual function D15:0 Output Output PC1 Input PC0 DELOP Output DS I/O CE Input Input R/W PROG I/O CLK Input BIN Output OVR Output RES Input SINGLE Input MASTER ...
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CE DS R/W PC0 PROG MASTER SINGLE CONTROL DELOP HRES Y IP7:0 DELAY BYPASS DELAY DELAYS Y L7:0 DELAY DELAYS PC1 RES CS3:0 DELAY COEFFICIENT STORE (64) 1 LINE 3 LINE 8 8 ARRAY OF MACs 4 LINE CLK Fig. ...
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Fig. 3a Pin connections for 84 I/O pin grid array package - AC84 (Power ) (bottom view) Fig 3b Pin connections for 132 I/O ceramic power flatpack - GC132 (Power) (top view) Fig 3 Pin connection ...
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Pin Signal Pin IP2 IP1 IP0 BYPASS X15 D1 N/C N3 X14 X13 N/C SINGLE ...
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BASIC OPERATION The PDSP16488A convolver performs a weighted sum of all the pixels within two dimensional window. Each pixel value is multiplied by a signed coefficient, or weight, and the products are summed together. In practice positive ...
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IP7:0 512 BYPASS 512 512 512 8 8 BYPASS ARRAY 512 512 512 512 L7:0 IP7:0 1024 BYPASS 4 4 1024 1024 ARRAY 1024 L7:0 To support real time applications an option is provided in which the ...
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WINDOW LINE LINE N C8 LINE WINDOW LINE N 2 C48 C49 C50 C51 LINE C10 C11 LINE N C40 C41 C42 C43 LINE N 1 ...
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Gain Control Block This block is provided as an aid to locating the bits of interest in the 32-bit internal result. The magnitude of the largest convolved output will depend on the size of the window, and the coefficient values ...
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INPUT 0 REG DELAYS 0 DELAY = 0, DEFINED BY REG D3 DELAYS WIDTH = S LINE DELAYS 0 ZERO DELAYS 4 CLOCK REG DELAYS 0 REG DELAYS D ...
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The data from the last device in a horizontal row of convolvers feeds the expansion input of the first device in the next row. This is shown in Fig. 7. With this arrangement, the position of the partial window as ...
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IP7:0 512 512 512 512 512 512 512 512 L7:0 IP7:0 L7:0 512 512 MSB LSB 512 512 512 512 512 512 IP7:0 1024 1024 1024 1024 L7:0 IP7:0 L7:0 512 512 16 MSB LSB C0 C16 512 512 16 ...
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Loading Registers from a Host CPU The X14:0 expansion data inputs on a single or master device are connected to the host bus to provide address and data for the internal registers multiple device system the remaining devices ...
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EPROM control lines X7:0 8 bit data from the EPROM to the Master or Single device. Otherwise data is received from the previous device in the chain. X14:8 Lower 7 address bits to the EPROM from a Master or Single ...
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BIT 7 This bit controls the bypass option on the first line delay on the L7:0 inputs only effective when an 8 bit pixel mode is selected, which also needs more than four line delays. When L7:0 are ...
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ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated 5V±10%, GND = 0V (Military) = 55°C to AMB Static Characteristics Characteristic Output high voltage Output low voltage ...
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Pin Pin Voltage A1 L2 GND GND C1 N2 GND D2 M3 GND D1 N GND E1 N4 GND F2 M5 GND G2 N5 GND G1 M6 5· N/C J1 ...
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Switching Characteristics for Host mode Characteristic DS hold time after REPLY low Host address/data setup time Read setup time to prevent Write Host signal hold time Expansion in to data out in PROG mode Delay from DS low to low ...
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Switching Characteristics for EPROM mode Characteristic Delay from DS low to Master PC1 Delay from low to DS high PC0 Delay from DS high to high PC1 DS high time DS high to new EPROM address EPROM data setup time ...
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Switching Characteristics, operational timings Characteristic CLK low time CLK high time Data in setup time Data in hold time CLK rising to output delay L7:0 output delay HRES low setup time Output enable time Output disable time X15:0 Expansion setup ...
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APPLICATIONS INFORMATION Device Requirements The number of devices required to implement a given convolver window depends on the size of the window, the required pixel rate, and whether the pixel accuracy bits. In practice ...
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The least significant 8 bits of the pixel are connected to the Master device and the most significant 8 bits are connected to the device producing the final result.. The internal sum in this device must be delayed by four ...
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EPROM V 15k NOM GND GND HRES SYNC BYPASS V DD PDSP16488A PIXEL IP7:0 DATA LEAST SIG BYTE OF L7:0 16-BIT PIXEL Non-interlaced EPROM mode HOST CPU O/C HRES SYNC BYPASS V DD PDSP16488A PIXEL IP7:0 DATA LEAST SIG L7:0 ...
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PIXEL DATA SYNC PIXEL CLOCK RESET SYNC ODD FIELD PIXEL CLOCK RESET 8-BIT PIXEL DATA 24 EPROM MSB GND IP7:0 PC0 PDSP16488A GND R HRES WINDOW V CLK BYPASS DD L7:0 RES V DD 15k NOM IP7:0 ...
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PIXEL DATA GND SYNC PIXEL CLOCK CLK V DD O/C RESET RES V DD 15k NOM MSB GND GND O/C LSB SYNC ODD FIELD PIXEL CLOCK CLK LSB RESET RES MSB FIELD DELAY V DD 16-BIT PIXEL DATA MSB ...
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PIXEL DATA PIXEL CLOCK CLK SYNC HRES IP7:0 RESET RES DS R/W HRES V DD BYPASS L7:0 IP7:0 PC0 DS R/W HRES GND BYPASS L7:0 26 REPLY HOST CPU ADDRESS DECODE PROG CE1 CE2 CE3 CE4 O/C IP7:0 PC1 PC0 ...
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EPROM V DD 15k ADDR BITS NOM PIXEL DATA PIXEL CLOCK CLK GND SYNC HRES RESET RES IP7:0 DS PDSP16488A GND R/W HRES V BYPASS DD FIELD DELAY IP7:0 PC0 DS PDSP16488A GND R/W HRES BYPASS ODD FIELD UPPER ALS138 ...
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MSB 16-BIT PIXEL DATA PIXEL CLOCK CLK SYNC HRES MSB IP7:0 RESET RES DS R/W HRES V DD BYPASS L7:0 LSB LSB FIELD DELAY MSB MSB IP7:0 DS R/W HRES ODD FIELD BYPASS L7:0 LSB LSB 28 REPLY HOST CPU ...
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EPROM V DD 15k NOM PIXEL DATA PIXEL CLOCK CLK O/C SYNC HRES RESET RES IP7:0 MASTER DS PDSP16488A R/W GND HRES V BYPASS DD L7:0 IP7:0 PC0 DS PDSP16488A R/W GND HRES GND BYPASS L7:0 IP7:0 PC0 DS PDSP16488A ...
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PIXEL CLOCK CLK SYNC HRES RESET RES PIXEL EPROM DATA O/C IP7:0 CS3 MASTER DS PC1 PDSP16488A R/W PROG GND (1) CE HRES V BYPASS RES DD L7:0 4 CLK DELAYS IP7:0 PC1 PROG DS PDSP16488A GND R/W (4) CE ...
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