DSP201 Burr-Brown Corporation, DSP201 Datasheet - Page 9

• Manufacturer Part Number: DSP201
• Description: DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS
• Manufacturer: Burr-Brown Corporation

Cascade Mode, but internal digital overhead requires addi-
tional Data Transfer Clock cycles before a new Convert
Command can be sent. The minimum time between Convert
Commands is 24 times the Data Transfer Clock period for
either the DSP201 or the DSP202 in standard modes, and 40
times the Data Transfer clock period for the DSP202 in the
Cascade Mode. There is no maximum time between Convert
Commands.
These additional clock cycles are used to set up the internal
shift registers and logic, and are included in the specifica-
tions for maximum update rate. This means a 12MHz Bit
Clock can achieve the maximum specified update rate of
500kHz.
DATA SYNCHRONIZATION
The DSP201 and DSP202 have internal logic to generate a
synchronization pulse (SYNC on pin 11) to signal the host
processor to transmit data. The synchronization pulse is sent
when a Convert Command is received, and the SYNC output
changes on the rising edge of XCLK. Timing is shown in
Figure 1.
The synchronization pulse can be programmed to be either
active High or active Low, depending on the logic level
input on SSF (Select Sync Format on pin 9.) If SSF is LOW,
SYNC will be normally HIGH, and will transmit a LOW
pulse after a Convert Command is received. If SSF is HIGH,
SYNC will be normally LOW, and will transmit a HIGH
pulse after a Convert Command is received. The SYNC
pulse will be as wide as one clock cycle on the Data Transfer
Clock input on XCLK (pin 12.)
SELECTING WORD LENGTH
If the Select Word Length input (SWL, pin 10) is HIGH, the
DSP201 or DSP202 will accept 16 bits of data after a Convert
Command, with the timing shown in Figure 1. After these 16
bits, additional data on SIN (DSP201 pin 13) or SINA and
SINB (DSP202 pins 13 and 14) will be ignored. Transparent
to the user, the internal shift register will append two zeroes
to the 16-bit data words before updating the D/As on the next
Convert Command.
If SWL is LOW, the DSP201 or DSP202 will clock 18 bits
of data into the internal shift register after a Convert Com-
mand, with the timing shown in Figure 1. Subsequent data
on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins
13 and 14) will be ignored.
In the 16-bit mode, an increment of 1 LSB will change the
D/A output by approximately 91.6 V (the 6V full scale
range divided by 2
change the output approximately 22.9 V (6V/2
The DSP201 and DSP202 analog performance is tested in
production using the 16-bit mode (with SWL HIGH), and
the typical performance curves were generated using the 16-
bit mode. Verification is made during final test that the 18-
bit mode functions, but the extra resolution of these last two
bits is not used when testing the analog performance.
16
), while an LSB in the 18-bit mode will
18
).
9
DSP202 CASCADE MODE
If CASC on the DSP202 (pin 16) is HIGH, the Cascade
Mode is implemented. In this mode, SINA (pin 13) and
SINB (pin 14) are strapped together and connected to the
serial output port of an appropriate DSP IC or other data
word source. A Convert Command initiates the transfer of a
32-bit word to the DSP202.
In the Cascade Mode, care must be taken to make sure SWL
(pin 10) is HIGH.
LATCH ENABLE
If ENABLE (pin 17) is LOW, the D/A outputs will be
latched with new data on the falling edge of the Convert
Command. Taking ENABLE HIGH causes the DSP201 or
DSP202 to ignore Convert Commands. With ENABLE
HIGH when a Convert Command arrives at time t, data
latched in the internal shift register after the Convert Com-
mand at t – 1 is not latched to the D/As, but a new
synchronization pulse is still generated and the data in the
shift register is overwritten. This feature allows multiple
DSP201s or DSP202s to share a single DSP IC and still be
independently updated.
RESET
Taking RESET (pin 8) LOW will cause the D/As to output
0V after two Convert Commands are received. The two
Convert Commands clear out the internal shift registers, and
data input on the serial input lines will be ignored while
RESET is low. This facilitates designing an analog output
system that goes into a known, benign state either at power-
up, after fault conditions or during a calibration cycle.
ENABLE (pin 17) must be LOW when resetting the DSP201
or DSP202 outputs to 0V.
After RESET is taken HIGH, two Convert Commands are
required before the output will relate to the input data. Also,
ENABLE must be LOW for the data to be latched to the D/As.
The first Convert Command again latches the outputs at 0V,
and the second Convert Command drives the output to the
level determined by the data clocked in after the first Convert
Command.
A RESET command after power up is not required for proper
operation of the DSP201 or DSP202.
LAYOUT CONSIDERATIONS
Because of the high resolution, linearity and speed of the
DSP201 and DSP202, system design problems such as
ground path resistance, contact resistance and power supply
quality become very important.
GROUNDS
To achieve the maximum performance from the DSP201 or
DSP202, care should be taken to minimize the effect of
current flows in the system grounds that may corrupt the
output voltages generated by the D/As. Pin 22 on the
DSP201 and pins 4 and 22 on the DSP202 are the most
DSP201/202
®