LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 8

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LM3S102-IRN20

Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
List of Figures
Figure 13-12. Master Burst SEND after Burst RECEIVE............................................................................... 271
Figure 13-13. Slave Command Sequence..................................................................................................... 272
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 18-6.
Figure 18-7.
Figure 18-8.
Figure 18-9.
Figure 18-10. Power-On Reset Timing .......................................................................................................... 327
Figure 18-11. Brown-Out Reset Timing ......................................................................................................... 327
Figure 18-12. Software Reset Timing ............................................................................................................ 327
Figure 18-13. Watchdog Reset Timing .......................................................................................................... 328
Figure 18-14. LDO Reset Timing ................................................................................................................... 328
Figure 19-1.
8
Analog Comparator Module Block Diagram ............................................................................ 296
Structure of Comparator Unit................................................................................................... 297
Comparator Internal Reference Structure ............................................................................... 298
Pin Connection Diagram.......................................................................................................... 307
Load Conditions....................................................................................................................... 319
I
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 322
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 323
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 323
JTAG Test Clock Input Timing................................................................................................. 325
JTAG Test Access Port (TAP) Timing ..................................................................................... 325
JTAG TRST Timing ................................................................................................................. 325
External Reset Timing (RST)................................................................................................... 327
28-Pin SOIC Package ............................................................................................................. 329
2
C Timing................................................................................................................................ 321
Preliminary
October 6, 2006

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