DS90CR213MTD National Semiconductor, DS90CR213MTD Datasheet
DS90CR213MTD
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DS90CR213MTD Summary of contents
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... Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in required cable Block Diagrams DS90CR213 Order Number DS90CR213MTD See NS Package Number MTD48 TRI-STATE ® registered trademark of National Semiconductor Corporation. ...
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Pin Diagrams DS90CR213 Typical Application www.national.com PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv DS012888-21 2 Proof DS90CR214 DS012888-22 DS012888-23 2 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. LVDS Receiver Input Voltage −0. LVDS Driver Output Voltage − ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter RECEIVER SUPPLY CURRENT I Receiver Supply Current CCRW Worst Case I Receiver Supply Current CCRZ Power Down Note 1: “Absolute Maximum Ratings” are those values beyond ...
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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol RCOP RxCLK OUT Period ( Figure 7 ) RCOH RxCLK OUT High Time ( Figure 7 ) RxCLK OUT Low Time ( Figure 7 ) RCOL ...
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AC Timing Diagrams FIGURE 4. DS90CR213 (Transmitter) Input Clock Transition Time = 0V Note 8: Measurements at V diff Note 9: TCSS measured between earliest and latest LVDS edges. Note 10: TxCLK Differential Low High Edge FIGURE 5. DS90CR213 (Transmitter) ...
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AC Timing Diagrams (Continued) FIGURE 8. DS90CR213 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR214 (Receiver) Clock In to Clock Out Delay FIGURE 10. DS90CR213 (Transmitter) Phase Lock Loop Set Time FIGURE 11. DS90CR214 (Receiver) Phase Lock Loop ...
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AC Timing Diagrams FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR283) www.national.com PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv (Continued) FIGURE 12. Seven Bits of LVDS in Once Clock Cycle FIGURE 14. Transmitter Powerdown Delay ...
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AC Timing Diagrams (Continued) FIGURE 16. Transmitter LVDS Output Pulse Position Measurement SW—Setup and Hold Time (Internal Data Sampling Window) TCCS—Transmitter Output Skew RSKM Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle) Cable Skew—Typically 10 ps–40 ps ...
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DS90CR213 Pin Description—Channel Link Transmitter Pin Name I/O No. PLL PLL GND I 2 LVDS LVDS GND I 3 DS90CR214 Pin Description—Channel Link Receiver Pin Name I/O No. RxIN RxIN− ...
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Applications Information ommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. BOARD LAYOUT: To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be ...
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Applications Information POWER SEQUENCING AND POWERDOWN MODE: Out- puts of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 3V. Clock and data outputs will begin to toggle 10 ms after V the Powerdown pin is above ...
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THIS PAGE IS IGNORED IN THE DATABOOK PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv 13 Proof 13 13 ...
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