DS92LV1260TUJB National Semiconductor, DS92LV1260TUJB Datasheet

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DS92LV1260TUJB

Manufacturer Part Number
DS92LV1260TUJB
Description
Six Channel 10 Bit BLVDS Deserializer
Manufacturer
National Semiconductor
Datasheet

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© 2003 National Semiconductor Corporation
DS92LV1260
Six Channel 10 Bit BLVDS Deserializer
General Description
The DS92LV1260 integrates six deserializer devices into a
single chip. The chip uses a 0.25u CMOS process technol-
ogy. The DS92LV1260 can simultaneously deserialize up to
six data streams that have been serialized by the National
Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS se-
rializers. The device also includes a seventh serial input
channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates inde-
pendently with its own clock recovery circuitry and lock-
detect signaling.
The DS92LV1260 uses a single +3.3V power supply with a
typical power dissipation of 1.2W at 3.3V with a PRBS-15
pattern. Refer to the Connection Diagrams for packaging
information.
Block Diagram
DS200002
Application
Features
n Deserializes one to six BusLVDS input serial data
n Seven selectable serial inputs to support n+1
n Seventh channel has single pin monitor output that
n Parallel clock rate up to 40MHz
n On chip filtering for PLL
n Absolute maximum worst case power dissipation =
n High impedance inputs upon power off (V
n Single power supply at +3.3V
n 196-pin LBGA package (Low-profile Ball Grid Array)
n Industrial temperature range operation: −40˚C to +85˚C
streams with embedded clocks
redundancy of deserialized streams
reflects input from seventh channel input
1.9W at 3.6V
package
cc
www.national.com
August 2003
= 0V)
20000202

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DS92LV1260TUJB Summary of contents

Page 1

... The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information. Block Diagram © 2003 National Semiconductor Corporation Features n Deserializes one to six BusLVDS input serial data streams with embedded clocks n Seven selectable serial inputs to support n+1 ...

Page 2

... LBGA: JC Storage Temp. Range Junction Termperature Electrical Characteristics Basic functionality and specifications per deserializer channel will be similar to National Semiconductor’s DS92LV1212A. Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2) Symbol Parameter LVCMOS/LVTTL DC Specifications: V High Level Input Voltage ...

Page 3

... Electrical Characteristics Basic functionality and specifications per deserializer channel will be similar to National Semiconductor’s DS92LV1212A. Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2) Symbol Parameter t REFCLK Transition Time RFTT Deserializer Switching Characteristics t RCLK Period RCP t RCLK Duty Cycle ...

Page 4

AC Timing Diagrams and Test Circuits www.national.com FIGURE 1. Deserializer Delay t DD 20000207 FIGURE 2. Output Timing t and t ROS ROH FIGURE 3. Locktime from PWRDN * t DSR1 4 20000204 20000209 ...

Page 5

AC Timing Diagrams and Test Circuits (Continued) FIGURE 4. Locktime to SYNCPAT t FIGURE 5. Unlock FIGURE 6. Deserializer Data Valid Out Times 5 20000211 DSR2 20000213 20000231 www.national.com ...

Page 6

AC Timing Diagrams and Test Circuits FIGURE 7. Deserializer TRI-STATE Test Circuit and Timing www.national.com (Continued) 6 20000218 ...

Page 7

Block Diagram Control Pins Truth Table PWRDN REN SEL2 SEL1 SEL0 Rout CHTST L Din6 Decoded to Din0 (not Rout 0 (0:9)(Note decoded) 11) H Din6 Decoded to ...

Page 8

... Functional Description The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream from National Semiconductor’s DS92LV1021 or DS92LV1023 Serializer. The deserializers then recover the clock and data to deliver the resulting 10-bit wide words to the outputs. A seventh serial data input provides n+1 redun- dancy capability ...

Page 9

Data Transfer (Continued) The Deserializer input pins are high impedance during Pow- erdown (PWRDN low) and power-off (V Resynchronization Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the em- bedded clock ...

Page 10

... USING THE DS92LV1021 AND DS92LV1260 The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream up to 480 Mbps from National Semiconductor’s DS92LV1021 or DS92LV1023 Serializer. The deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the output ...

Page 11

Application Information • Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals). Power system performance may be greatly improved by using thin dielectrics ( mils) for power/ground sandwiches. This increases the intrinsic ...

Page 12

FIGURE 10. Using t DJIT www.national.com FIGURE 8. Typical Applications Circuit FIGURE 9. Failsafe Biasing Setup and t to Generate an Eye Pattern Mask and Validate Signal Quality RNM 12 20000230 20000227 20000228 ...

Page 13

FIGURE 11. Random Lock Hot Insertion 13 20000215 www.national.com ...

Page 14

Pin Diagram www.national.com Top View of DS92LV1260 (196 pin LBGA) 14 20000214 ...

Page 15

Pin Descriptions Pins Pin Name B2,B14 GND C12,C13,B13 SEL (0:2) A4-A3, C6-C5, A7-A6, C9-C8, A10-A9, Rin(n) +/- C11-C10, A13-A12 D12 PVdd F12 AVdd B12,A14,D10 PGND B11 AGND C7 AVdd B9 AVdd A11 AVdd B7 AGND A8 AGND B8 AGND A5 ...

Page 16

Pin Descriptions (Continued) Pins Pin Name K3, K4, H3, H4, H2, G4, G3, F4, E4, E2, J3, L3, J2 ,L1 ,K2 ,M1 ,N1 ,N2 ,M2 ,M3 ,M7 ,L6 ,N6 ,M6 ,P4, M5, P3, N4, P2, M4, M8, L8, N9, M9, ...

Page 17

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) Order Number DS92LV1260TUJB NS Package Number UJB196A 2. A critical component is any component of a life ...

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