AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 11

• Manufacturer Part Number: AN1740
• Description: Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
• Manufacturer: Freescale Semiconductor / Motorola

Comparator 2
AN1740
MOTOROLA
Comparator 2 is a basic voltage comparator with its positive input tied
permanently to the PB0 pin and its negative input being tied to a number
of internal or external functions. The negative input of comparator 2 can
be switched to various sources, but in all cases the internal sample
capacitor of approximately 10 pF will remain connected from the
negative input to V
and static flag bits in the ASR located at address $001E. The dynamic
output bit, CMP2, follows the output of the comparator regardless of its
prior conditions and becomes a logical 1 whenever the comparator’s
positive input is above its negative input. The static flag bit, CPF2,
becomes set whenever there is a rising output from the comparator and
remains set until cleared by writing a logical 1 to the reset bit, CPFR2.
Therefore, the CPF2 bit can be used to capture events where the
comparator’s positive input rose above its negative input.
Not only does comparator 2 allow software subroutines polling the
CMP2 or CPF2 bits or an analog interrupt caused by CPF2 being set,
the CPF2 flag bit also can trip the input capture function of the 16-bit
timer if the ICEN bit is set in the ACR at location $001D.
Comparator 2 has limited connection capabilities versus comparator 1.
The primary purpose of comparator 2 is to construct a multiple channel
integrating A/D convertor using the internal channel MUX, internal
references, input divider, and sample and hold. Comparator 2 can be
used as a simple comparator as shown in
similar to cases 1, 4, and 5 for comparator 1 shown in
However, due to the internal resources, comparator 2 has several
unique cases of its own. These additional cases are shown in
and are described in the following paragraphs.
Case 6 uses comparator 2 to monitor an outside function on PB0 with
respect to the divided input on PB1, PB2, PB3, or PB4. In this case, the
user should configure the PB1:PB4 input selected to be an input with its
pulldown deactivated. The divider nominally divides the input by 2 which
allows the selected PB1:PB4 pin to be tied to a voltage level up to V
To activate the divider, the DHOLD MUX must be enabled.
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SS.
Its output can be monitored by the dynamic output
Figure
4. These uses are
Voltage Comparators
Figure
Application Note
3.
Figure 5
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