AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 32

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

As seen in , the WE signal extends beyond the CS assertion interval. For devices which require particular
relationships between CS and WE, AS can be used with simple logic to adjust the relationships for such I/O
or Flash/ROM devices. Examples are shown in Figure 24.
Using the logic shown above, the ROM/I/O timing can be adjusted as shown in Figure 25.
This logic is often useful with flash memory and other devices which require extra time after the chip-select
for recovery, or those which will not allow WE asserted concurrently with CS. Note, though, that since AS
timing values must be programmed into the MCCR registers, this solution is not suitable for code that must
be available immediately after reset (i.e., startup code in RCS0).
1.10 Reset
A system using the MPC107 must provide it with a proper reset signal; the MPC107 requires a reset pulse
that is at least 100 µs (for PLL stabilization) plus 255 PCI bus clocks in duration. For systems connected to
the PCI bus, the PCIRST# signal easily meets this restriction since PCI guarantees a reset assertion period
of 1 ms.
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MPC107
MPC107
A19-A0
RCSx
RCSA
WEB
DATA
CLK
WE
RCSx
RCSx
WE
WE
AS
AS
Figure 24. MPC107 PortX Signal Adjustments
Figure 25. PortX-Modified I/O Timing
ASFALL
MPC107 Design Guide
LV32
LV32
ASRISE
RCSA
WEB
WE
CS
WE
CS
FLASH “B”
FLASH “A”