AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet - Page 5

• Manufacturer Part Number: AN1934
• Description: Effects of Skew and Jitter on Clock Tree Design
• Manufacturer: Freescale Semiconductor / Motorola

PLL Bandwidth and Jitter
and maintains an output frequency based upon that reference
frequency. If the reference frequency changes, the PLL
attempts to follow the change in the reference frequency.
However, if the change is faster than the PLL can follow, the
PLL based clock driver acts as a low pass filter and ignores or
effectively filters out the higher frequency changes on its input.
As with any low pass filters, the PLL has a cutoff frequency, or
bandwidth, associated with it. This bandwidth becomes
important to our clock tree design. High frequency noise and
jitter will not pass through the PLL.
many factors, including the feedback divider ratio. The higher
the divide ratio, the lower the bandwidth. Thus, those PLL clock
driver devices that have selectable feedback divide ratios will
MOTOROLA
The PLL based clock driver locks on to a reference frequency
The actual bandwidth of the locked PLL is dependent on
Figure 10.
Period Jitter for Typical PLL Clock Device with F
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have varying bandwidth values. Bandwidth may or may not be
specified by the PLL clock driver manufacturer. If not specified,
the information is usually available on request.
waveform. Note the cutoff frequency is about 300 kHz. As
mentioned before, the cutoff frequency will vary with a change
in the divide ratio in the feedback loop. Bandwidths of
PLL–based clock drivers vary from low values of a few kHz to
higher values of a MHz or more depending upon the intended
application of the device. Clock synthesizers typically have the
lowest bandwidth. Bandwidths of these devices are in the order
of 30 to 50 kHz. Clock generators are next with bandwidths of
a few hundred kHz. The devices with the highest bandwidth are
the Zero–Delay–Buffers. The bandwidths of these devices are
typically a MHz and above.
Figure 11 is a typical PLL frequency modulation bandwidth
OUT
= 400 MHz
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