AN2077 Motorola / Freescale Semiconductor, AN2077 Datasheet - Page 13

• Manufacturer Part Number: AN2077
• Description: PowerPC Design Checklist
• Manufacturer: Motorola / Freescale Semiconductor

1.3 L2 Cache SRAM Connections
The MPC750, MPC755 and MPC74X0 processors support a “backside” L2 cache on a private cache bus.
The L2 interface uses standard asynchronous, pipelined burst or late-write SRAM devices in a
non-pipelined manner. The connections are shown in the following table:
In addition, the L2SYNC_OUT pin should be connected to the L2SYNC_IN pin using a trace length equal
to the ones used on the L2CLK_OUT(A:B) traces.
SRAM Signal
SB(A:D)
DP(0:7)
D(0:63)
A(16:0)
ADSC
ADSP
SGW
ADV
LBO
SE1
SE2
SE3
A17
A18
SW
OE
CK
ZZ
G
K
L2ADDR(16:0)
L2ADDR17
L2ASPARE
L2OVDD
GND
L2OVDD
L2DATA(0:63)
L2DP(0:7)
GND
L2CLK_OUTA
L2CLK_OUTB
GND or VCC
GND or L2OVDD
L2WE
L2OVDD
L2CE
L2OVDD
GND
L2ZZ or GND
Connection
Table 3. L2 Cache SRAM Connections
Connect buses; order is not important since burst mode is not used.
If present and/or needed. For forward compatibility, tie to a weak (1K-10K
pulldown) since LA17 = CE3 on some SRAM devices.
If present and/or needed.
Deasserted since burst mode not used.
Asserted to continually accept addresses.
Deasserted since burst mode not used.
Connect buses; order is not important since byte access modes are not
used. DP bits may be intermixed with D bits if and only if parity-capable
SRAMs are always used; otherwise, connect DP only to DP.
Connect buses; order is not important since byte access modes are not
used. DP bits may be intermixed with D bits. DP bits may be intermixed
with D bits if and only if parity-capable SRAMs are always used; otherwise,
connect DP only to DP.
Since the L2 is chip-select-controlled, it is normally in output mode unless
being written to. OE may tied low.
For single-ended clocks, tie one clock to each of two SRAMs without
sharing. Keep trace lengths matching other L2 traces.
For differential clocks, tie “A” to the active high clocks and “B” to the active
low clocks. Route the clocks in a “Y” manner so the stubs have the same,
minimal, length.
GND is for PowerPC bursts order; however, burst mode is not used so may
be tied high or low.
Byte write modes are not used.
Write cause global writes.
Byte write modes are not used.
Connect SRAM chip select.
Second chip-select not used.
Third chip-select not used.
Optional; not all SRAMs have ZZ.
PowerPC Design Checklist
Notes
L2 Cache SRAM Connections
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