AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 11

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

3.2 USIU Interrupt Controller
At the end of the interrupt routine, executing a return from interrupt (rfi) instruction restores the context
by hardware. This causes the action shown in
The main interrupt controller is in the USIU module. However, there are interrupt controller functions in
other areas, such as the level mapping of peripherals in the UIMB module (see
Sources: UIMB
The USIU interrupt controller has 16 inputs: eight external interrupt request pins (IRQ[0:7]) and eight
internal interrupt “levels”. As mentioned in
mapping mechanism for interrupt sources and imply a priority. Interrupt sources inside the USIU (time
base, real-time clock, PIT and PLL change of lock detector) are assigned a level 0:7. Interrupt sources
from peripherals on the IMB3 bus can have levels 0:31. However, these IMB3 bus peripherals with lev-
els 7:31 are all mapped to level 7 of the USIU interrupt controller (see
USIU Internal
The 16 USIU interrupt controller inputs (8 pins and 8 levels) are fed into the SIPEND (USIU interrupt
pending register). Software can read this register to see which of the 16 interrupts are pending.
Register/Pointer
Instruction
Pointer
MSR
The MPC565 and other future MPC5xx family members have an enhanced inter-
rupt controller that is backwards compatible to the MPC555. The new features
must explicitly be enabled.
Devices).
Peripherals).
MSR[16:31] gets re-loaded from SRR1 (enabling external interrupts, other
maskable exceptions, etc. again.)
Gets re-loaded from SRR0, which resumes program execution after the last
executed instruction before the interrupt was recognized.
Freescale Semiconductor, Inc.
Table 7 Return From Interrupt Context Switch
SPR
80
81
82
For More Information On This Product,
Table 6 Manipulating EE and RI Bits
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
Mnemonic
NRI
EIE
EID
Section 2.2 Interrupt Sources and
NOTE
Table
MSR[EE]
7.
Action
1
0
0
MSR[RI]
1
1
0
Section 3.4 Interrupt Sources:
Section 3.6 Interrupt
Levels, levels are a
MOTOROLA
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