AN2127 Freescale Semiconductor / Motorola, AN2127 Datasheet - Page 2

• Manufacturer Part Number: AN2127
• Description: EMC Guidelines for MPC Based Automotive Powertrain Systems
• Manufacturer: Freescale Semiconductor / Motorola

2.2 ENGCLK
2.3 System Frequency
2.4 Power Management
2.5 Bus Configuration
this results in the selection of full drive strength. Full drive strength for CLKOUT assumes a load of 90
pF and is intended for test purposes only. Unless full drive strength is required for timing considerations,
it is recommended that a reduced drive strength be used. The MPC55x and the MPC56x have half-drive
strength options. The MPC56x also has a quarter-drive strength option with additional control bit,
CQDS, in the SCCR register.
Additionally, the COM bits can be configured to disable the CLKOUT driver. If CLKOUT is not needed
in the system, it is strongly recommended that it be disabled. The maximum output frequency for CLK-
OUT is equal to the system operating frequency.
The ENGCLK driver has software selectable drive strength and frequency options. The frequency of
ENGCLK is determined by the ENGDIV bits in the SCCR register. The default is set for a maximum
division which results in the lowest possible frequency. The ENGCLK should be configured for the low-
est possible frequency that is required by the system. Additionally, the ENGCLK driver has selectable
output drive strength options which are controlled by the EECLK bits in the SCCR register. For the
MPC55x, the ENGCLK can be enabled at full-drive strength (90 pF), enabled at half-drive strength (45
pF), or disabled.
It is recommended that ENGCLK be disabled or used in half-drive strength mode. For the MPC56x, the
ENGCLK driver can be enabled with a 2.6-V output, enabled with a 5.0-V output, or disabled. The
MPC56x does not have a half-drive strength option. It is recommended that the ENGCLK be disabled
or used with the 5.0-V output; the 5.0-V output drives slower than the 2.6-V output.
System frequency is determined by the crystal frequency and the PLL multiplication factor. The PLL
multiplication factor is set by the MF bits in the PLPRCR register. In general, the lowest possible fre-
quency should be used. However, since radiated emissions will occur at the fundamental frequency and
harmonics of the fundamental some care should be taken to avoid having the second harmonic fall in
the radio broadcast range.
Many individual modules have the option to be disabled. Disabling a module reduces SSN currents be-
cause the transistors in the disabled module are no longer clocked. All modules which are not used
should be disabled by setting the STOP bit in each module’s MCR register.
Bus pins have two drive strength options: full-drive and reduced-drive. These options are controlled by
the COM bits in the SCCR register. Reduced drive should be used unless full-drive strength is required
to meet system timing specifications. Additionally, if the bus is not needed, the MCU should be config-
ured for single-chip mode operation (i.e., address and data buses not used). Single-chip mode is con-
figured by the hard reset configuration word. The bus also has a show cycle feature which when enabled
drives the contents of the internal bus onto the external bus pins. Show cycles should be disabled.
EMC Guidelines for MPC500-Based Automotive Powertrain Systems
The MPC555 K62N (Revision M) or later has a one-third instead of one-half drive
strength option.
The MPC555 K62N (Revision M) or later has drive strengths of 50 pF (full) and 25
pF (half).
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 15 July 2001
Go to: www.freescale.com
NOTE
NOTE
MOTOROLA
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