AN2316 Freescale Semiconductor / Motorola, AN2316 Datasheet

AN2316

Manufacturer Part Number

AN2316

Description

Connecting an MSC8102 TDM to a Time-Slot Interchange Switching Device

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

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Application Note

AN2316/D

Rev. 0, 8/2002

Connecting an

MSC8102 TDM to a

Time-Slot Interchange

Switching Device

by Yael Kahil

CONTENTS

1 MSC8102 TDM to TSI I

1.1 Configuring the

1.2 Configuration

1.3 Channel Parameter

1.4 Control Registers ........ 5

1.5 External Interface ....... 6

1.6 TDM Activation........... 6

2 Configuring the

nterface .......................... 1

MSC8102 TDM.............. 2

PEF24471 (TSI) ............ 6

Registers...................... 3

Registers...................... 5

The MSC8102 time-division multiplex (TDM) interface enables many devices to communicate over a

single bus. Traffic is managed according to a TDM method in which only one device drives the bus

(transmit) for each channel. Each active device drives its active transmit channels and samples its active

receive channels. It is the system designer’s responsibility to guarantee that there is no conflict in transmit

channel allocation. The TDM interface consists of four identical and independent TDM modules, each

supporting 256 channels running at up to 50 Mbps with 2,4, 8, and 16-bit word size. The TDM bus

connects gluelessly to most T1/E1 frames as well as to common buses such as the H.110, SCAS, and

MVIP.

This document presents a test set-up example in which one MSC8102 TDM is connected to a time-slot

interchange device (TSI), in this case, the Infineon PEF24471. There are two data links per channel, each

with its own transmit and receive lines, thus doubling the amount of data that can be driven through the

system. This application note first describes the physical interface between the MSC8102 and the

Infineon PEF24471 (TSI) switching device and then it explains how to configure one MSC8102 TDM

module and the TSI.

An E1 interface is implemented using 32 × 64 Kbps slots, yielding a 2.048 Mbps bandwidth. Figure 1

shows MSC8102 TDM0 connected to ports 0 and 1 on the PEF24471 switching device. The TDM

interface is simple, consisting of a common clock for receive and transmit, a synchronization signal, and

data signals. The MSC8102 device receives clock (TDM0TCLK) and synchronization signals

(TDM0TSYN) from the PEF24471 device. The MSC8102 transmits data to the PEF24471 device

through ports TDM0TDAT and TDM0RCLK, and it receives data through ports TDM0RDAT and

TDM0RSYN. An internal loopback is achieved by setting CDR2 in the PEF24471 device to as value of

0x15 so that port IN0 connects to port OUT0 and port IN1 connects to port OUT1, as shown in Figure 1.

MSC8102 TDM to TSI Interface

Freescale Semiconductor, Inc.

For More Information On This Product,

TDM0

MSC8102

Go to: www.freescale.com

Memory Controller

Figure 1. MSC8102 to PEF24471(TSI) Interface

TDM0RSYN

TDM0TDAT

TDM0RCLK

TDM0RDAT

TDM0TSYN

TDM0TCLK

Infineon-PEF24471 Switching Device

IN1

OUT0

OUT1

IN0

GPCLK3

GPCLK2

Microprocessor

Interface

Loop 0

Loop 1

Related parts for AN2316

AN2316 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Application Note AN2316/D Rev. 0, 8/2002 Connecting an MSC8102 TDM to a Time-Slot Interchange Switching Device by Yael Kahil The MSC8102 time-division multiplex (TDM) interface enables many devices to communicate over a single bus. Traffic is managed according to a TDM method in which only one device drives the bus (transmit) for each channel ...

Page 2

Configuring the MSC8102 TDM The E1 frame is delimited by the switching (TSI) synchronization signal ( of the first time slot in the frame and by a clock ( split into multiple time slots, each designated for a different logical ...

Page 3

Freescale Semiconductor, Inc. 1.2 Configuration Registers Table 1 describes the TDM configuration registers that define the interface between the MSC8102 device and the TSI. The configuration register settings determine the signal polarity, timings, and device functionality. The TDM clocks are ...

Page 4

Configuring the MSC8102 TDM Table 2. Receive Frame Parameter Register (TDM0RFP) Settings (Continued) Bits fields Setting TDM0RFP[26–29]:RCS = 0X7 TDM0RFP[30]:RT1 = 0X0 TDM0RFP[31]:RUBM = 0X0 Register Setting Summary: Memory resource can become scarce as the number of TDM channels increases. ...

Page 5

Freescale Semiconductor, Inc. 1.3 Channel Parameter Registers The channel parameter registers determine the parameters of each channel, such as the buffer location, channel type, and channel activation. Channels that are not used should be clear. In this example the receive ...

Page 6

Configuring the PEF24471 (TSI) Bits fields Setting TDM0TDBST[TDBST] = 0x000038 TDM0RDBFT[RDBFT] = 0x000018 TDM0RDBST[RDBST] = 0x000038 Register Setting Summary: 1.5 External Interface The TDM interface is essentially a set of I/O pins that can configured for either a peripheral or ...

Page 7

Freescale Semiconductor, Inc. Table 7. TSI Configuration Description Set PDC and PFC as outputs. The PDC frequency is 2.048 MHz Define GPCLK2 as a frame sync. Define a s clock of frequency of 2.048 MHz for GPCLK3. Configure all the ...

Page 8

... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna and StarCore are trademarks of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2316/D For More Information On This Product, Go to: www.freescale.com ...

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