AN2347 Freescale Semiconductor / Motorola, AN2347 Datasheet
AN2347
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AN2347 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2347/D Rev. 0, 9/2002 Using an MPC8260 and an MPC7410 with Shared Memory Dave McCartney The MPC8260 PowerQUICC II one chip a high-performance MPC603e™ microprocessor, a very flexible system integration NCSG Applications unit, and many communications peripheral controllers that can be used in a variety of East Kilbride, applications, particularly in communications and networking systems ...
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Freescale Semiconductor, Inc. Features Features The main components consist of the MPC7410, the MPC8260 and the Tundra CA91L750 PowerPRO memory controller. These devices are connected using a standard 60x bus operating at 83MHz. The PowerPRO arbitrates control of the bus ...
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Freescale Semiconductor, Inc. 1.3 Interface Schematics A full set of schematics is provided in “Appendix A—Interface Schematics” on page 4. Figure 1-2 shows a top-level interconnect of the major system components followed by three top-level schematics that show ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics Appendix A—Interface Schematics PP_TA_N FLASH_RESET TBST_N ARTRY_N EE_AL2 EE_AL2 EE_AL1 EE_AL1 EE_SELECT SD_SELECT TEA_N TT[0:4] FLASH_WE_N EE_WE TSIZ[0:3] FLASH_OE_N EE_OE_N A[0:31] EE_DATA[0:7] EE_DATA[0:7] FLASH_CE_N EE_CS0_N DH[0:31] DL[0:31] DP[0:7] MCP_N INT_N BR0_N ...
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Freescale Semiconductor, Inc. MOTOROLA Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Appendix A—Interface Schematics Figure 1-3. MPC8260 Top Level Go to: www.freescale.com 5 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 6 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Figure 1-4. MPC7410 Top Level Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Figure 1-5. Tundra CA91L750 Top Level MOTOROLA Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Appendix A—Interface Schematics Go to: www.freescale.com 7 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 8 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product Figure 1-6. Shared Memory Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. Using an MPC8260 and MPC7410 with shared memory MOTOROLA Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Appendix A—Interface Schematics VDD 37 Figure 1-7. Boot Flash Go to: www.freescale.com 9 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 10 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Figure 1-8. MPC8260 Expansion Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Note: TSIZ0 should be pulled down to allow for when TSIZ0 is an input A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 10 Figure 1-10. MPC8260 COP Interface 12 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product to: www.freescale.com 4 16 10K ...
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Freescale Semiconductor, Inc. Figure 1-11. MPC8260 Parallel I/O Ports MOTOROLA Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Appendix A—Interface Schematics Go to: www.freescale.com 13 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 3 16 10K RN14B 4 16 10K RN14C 5 16 10K RN14D Figure 1-12. MPC8260 Local Memory 14 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics Figure 1-13. MPC8260 Power Connections 15 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics DH31 R5 DH31 DH30 U4 DH30 DH29 W3 DH29 DH28 V4 DH28 DH27 V5 DH27 DH26 P7 DH26 DH25 W4 DH25 DH24 U5 DH24 DH23 W5 DH23 DH22 U6 DH22 DH21 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics 1 Figure 1-15. MPC7410 COP Interface 17 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, R10 to: www.freescale.com 10K ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics L2DATA32 H13 L2D32 L2DATA33 G19 L2D33 L2DATA34 G16 L2D34 L2DATA35 G15 L2D35 L2DATA36 L2D36 G14 L2DATA37 G13 L2D37 L2DATA38 F19 L2D38 L2DATA39 F18 L2D39 L2DATA40 F13 L2D40 L2DATA41 E19 L2D41 L2DATA42 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics R13 Figure 1-17. MPC7410 L2 Cache SRAM 19 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, 4K7 1 2 R16 4K7 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics U9C D4 GND0 COREVDD0 D6 GND1 COREVDD1 D10 GND2 COREVDD2 D14 GND3 COREVDD3 D16 GND4 COREVDD4 E8 GND5 COREVDD5 E12 GND6 COREVDD6 F4 GND7 COREVDD7 F6 GND8 COREVDD8 F10 GND9 COREVDD9 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics DBG0_N DBG1_N PP_TA_N DH0 DH1 DH2 DH3 DH4 DH5 DH6 DH7 DH8 DH9 DH10 DH11 DH12 DH13 DH14 DH15 DH16 DH17 DH18 DH19 DH20 DH21 DH22 DH23 DH24 DH25 DH26 DH27 ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics Figure 1-20. Tundra CA91L750 Memory Interface 22 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics RN15K 10K 16 12 RN15J 10K 16 11 Figure 1-21. Tundra CA91L750 MSC + Test Interface 23 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This ...
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Freescale Semiconductor, Inc. Appendix A—Interface Schematics Appendix A—Interface Schematics Figure 1-22. Tundra CA91L750 Power Connections 24 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Appendix B—Initialization Software Appendix B—Initialization Software Note: The switch between pins 1 and 16 is spare SW1 DIP-8 Figure 1-23. POR Reset and Configuration Appendix B—Initialization Software This ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 .include "initPowerPro.h" Shared SDRAM Parameters REFINT .equ 984 _start insert other init code here # andis. r0,r0,0 andi. r0,r0,0 # make sure r0 is zero mfmsr r3 andi. r3,r3,0xffbf# ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 lis r1, _stack_addr@h/* _stack_addr is generated by linker */ ori r1, r1, _stack_addr initialize small data area pointers (EABI) */ lis r2, _SDA2_BASE_@h/* __SDA2_BASE_ is generated by linker */ ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 ori r7, r7, PowerPro_Base@l addi r4, r7, PB_GEN_CTRL # Set r4 as pointer to required register lwarx r3 ori r3, r3, 0x0005 stw r3, 0, (r4) addi r4, r7, ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 stw r3, 0, (r4) addi r4, r7, EE_B0_MASK# Set r4 as pointer to required register addis r3, 0, 0xFFF0 ori r3, r3, 0x0000 stw r3, 0, (r4) addi r4, r7, EE_B0_CTRL# ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 mtspr ibat0l, r4 mtspr ibat0u, r3 isync addis r3, 0, 0x0000 ori r3, r3, 0x1fff addis r4, 0, 0x0000 ori r4, r4, 0x0002 mtspr ibat1l, r4 mtspr ibat1u, r3 isync addis ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 addis r10, r0,(SIZ1M|CLK20|RAMSB|OH05|L2E|L2DO)@ha mtspr l2cr, r10 sync mfspr r5, hid0 ori r6, r5, 0x4400# Data cache only 0x4400 andi. r5, r6, 0xfbff# clear the invalidate bit 0x4000 mtspr hid0, r6 isync ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 addis r4, 0, 0xf000 ori r4, r4, 0x0022 mtspr dbat0l, r4 mtspr dbat0u, r3 isync addis r3, 0, 0xc000 ori r3, r3, 0x1fff addis r4, 0, 0xc000 ori r4, r4,0x0022 mtspr ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 isync addis r3, 0,0x0000 ori r3, r3, 0x1fff addis r4, 0, 0x0000 ori r4, r4, 0x0002 mtspr ibat1l, r4 mtspr ibat1u, r3 isync addis r3 mtspr ibat2u, r3 mtspr ...
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Freescale Semiconductor, Inc. Main Initialization Routine—P2N.2 Main Initialization Routine—P2N.2 addis r4, 0, 0xF000 sync addis r4, 0, 0xF001 # bl init_siu Configure EPIC addis r4, r0, 0xf804 ori r4, r4, 0x1020 addis r5, r0, 0x2000 stwbrx r5, r0, r4 mtspr ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h Required Header File—init_cn.h On-Chip Core Registers These values represent the special purpose registers used in this example. Refer to PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors manual for the ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h L2DF: .equ 0x4000 L2BYP: .equ 0x2000 L2IP: .equ 0x0001 MSR Bit Settings # High word POW: .equ 0x00040000 ILE: .equ 0x00010000 # Low word EE: .equ 0x8000 PR: .equ 0x4000 FP: ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h DOZE: .equ 0x00800000 NAP: .equ 0x00400000 SLEEP: .equ 0x00200000 DPM: .equ 0x00100000 NHR: .equ 0x00010000 # low word ICE: .equ 0x8000 DCE: .equ 0x4000 ILOCK: .equ 0x2000 DLOCK: .equ 0x1000 ICFI: ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h PVR: .equ 287 SPRG0: .equ 272 SPRG1: .equ 273 SPRG2: .equ 274 SPRG3: .equ 275 TBL_W: .equ 284 TBU_W: .equ 285 TBL_R: .equ 284 TBU_R: .equ 285 IBAT0U: .equ 528 IBAT0L: ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h IMISS: .equ 980 ICMP: .equ 981 # Instruction PTE Compare Register RPA: .equ 982 # Required Physical Address Register HID0: .equ 1008 # Hardware Implementation Register 0 HID1: .equ 1009 # ...
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Freescale Semiconductor, Inc. Required Header File—init_cn.h Required Header File—init_cn.h PPC_ACR: .equ 0x0028 MBMR: .equ 0x0174 MDR: .equ 0x0188 IDMR1: .equ 0x1024 RCCR: .equ 0x19C4 SIMR_H: .equ 0x0C1C SIMR_L: .equ 0x0C20 CPCR: .equ 0x19C0 IDMA Parameter RAM Definitions IBASE: .equ 0x0000 ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h R11_OFFSET: .equ (11*4) R12_OFFSET: .equ (12*4) SRR0_OFFSET: .equ (13*4) SRR1_OFFSET: .equ (14*4) LR_OFFSET: .equ (15*4) CTR_OFFSET: .equ (16*4) XER_OFFSET: .equ (17*4) CR_OFFSET: .equ (18*4) STACK_SZ: .equ (20*4) C_FRAME_SZ: .equ (4*4) Buffers ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h PB_GEN_CTRL: .equ 0x004 PB_ARB_CTRL: .equ 0x008 PB_ERR_ATTR: .equ 0x00C PB_ERR_ADDR: .equ 0x010 PB_AM: .equ 0x014 PB_AM_MASK: .equ 0x018 VERSION_REG: .equ 0x01C TEST_MODE_SELECT:.equ 0x01F SDRAM Registers SD_REFRESH: .equ 0x020 SD_TIMING: .equ 0x024 ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h # 0x07C FLASH/ROM Registers EE_B0_ADDR: .equ 0x080 EE_B0_MASK: .equ 0x084 EE_B0_CTRL: .equ 0x088 # 0x08C EE_B1_ADDR: .equ 0x090 EE_B1_MASK: .equ 0x094 EE_B1_CTRL: .equ 0x098 # 0x09C EE_B2_ADDR: .equ 0x0A0 EE_B2_MASK: .equ ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h General Purpose Timer Registers GPT0_COUNT: .equ 0x100 GPT0_CAPTURE: .equ 0x104 GPT1_COUNT: .equ 0x108 GPT0_INT: .equ 0x10C GPT0_ISTATUS: .equ 0x110 GPT1_CAPTURE: .equ 0x114 GPT1_INT: .equ 0x118 GPT1_ISTATUS: .equ 0x11C GPT0_T0: .equ 0x120 ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h GPT1_M3: .equ 0x17C Interrupt Controller Registers INT_STATUS: .equ 0x180 INT_MSTATUS: .equ 0x184 INT_ENABLE: .equ 0x188 INT_GENERATE: .equ 0x18C INT_POLARITY: .equ 0x190 INT_TRIGGER: .equ 0x194 INT_VBADDR: .equ 0x198 INT_VINC: .equ 0x19C INT_VECTOR: ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h UART1_SCR: .equ 0x1C7 # 0x1C8 # 0x1CC - 0x1DC PowerPro reserved General Purpose I/O Registers GPIO_A: .equ 0x1E0 GPIO_B: .equ 0x1E4 GPIO_C: .equ 0x1E8 GPIO_D: .equ 0x1EC GPIO_E: .equ 0x1F0 GPIO_F: ...
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Freescale Semiconductor, Inc. Required Header File—initPowerPro.h Required Header File—initPowerPro.h 47 Using an MPC8260 and an MPC7410 with Shared Memory For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2347/D For More Information On This Product, Go to: www.freescale.com ...